Lines Matching refs:MUX_CFG
452 #define MUX_CFG(_id, _offset, _shift, _witdh)\ macro
462 MUX_CFG(MUX_ADC1, RCC_ADC12CKSELR, 0, 2),
463 MUX_CFG(MUX_ADC2, RCC_ADC12CKSELR, 2, 2),
464 MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2),
465 MUX_CFG(MUX_DCMIPP, RCC_DCMIPPCKSELR, 0, 2),
466 MUX_CFG(MUX_ETH1, RCC_ETH12CKSELR, 0, 2),
467 MUX_CFG(MUX_ETH2, RCC_ETH12CKSELR, 8, 2),
468 MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2),
469 MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2),
470 MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
471 MUX_CFG(MUX_I2C3, RCC_I2C345CKSELR, 0, 3),
472 MUX_CFG(MUX_I2C4, RCC_I2C345CKSELR, 3, 3),
473 MUX_CFG(MUX_I2C5, RCC_I2C345CKSELR, 6, 3),
474 MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3),
475 MUX_CFG(MUX_LPTIM2, RCC_LPTIM23CKSELR, 0, 3),
476 MUX_CFG(MUX_LPTIM3, RCC_LPTIM23CKSELR, 3, 3),
477 MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
478 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3),
479 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3),
480 MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
481 MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2),
482 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2),
483 MUX_CFG(MUX_SAES, RCC_SAESCKSELR, 0, 2),
484 MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3),
485 MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3),
486 MUX_CFG(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3),
487 MUX_CFG(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3),
488 MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2),
489 MUX_CFG(MUX_SPI1, RCC_SPI2S1CKSELR, 0, 3),
490 MUX_CFG(MUX_SPI23, RCC_SPI2S23CKSELR, 0, 3),
491 MUX_CFG(MUX_SPI4, RCC_SPI45CKSELR, 0, 3),
492 MUX_CFG(MUX_SPI5, RCC_SPI45CKSELR, 3, 3),
493 MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2),
494 MUX_CFG(MUX_UART1, RCC_UART12CKSELR, 0, 3),
495 MUX_CFG(MUX_UART2, RCC_UART12CKSELR, 3, 3),
496 MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3),
497 MUX_CFG(MUX_UART4, RCC_UART4CKSELR, 0, 3),
498 MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3),
499 MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3),
500 MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1),
501 MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2),