Lines Matching +full:0 +full:x43000000
25 # define CONFIG_MACH_TYPE_COMPAT_REV 0
63 #define SDRAM_OFFSET(x) 0x2##x
64 #define CONFIG_SYS_SDRAM_BASE 0x20000000
65 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
66 #define CONFIG_SYS_TEXT_BASE 0x2a000000
70 #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
71 #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
73 #define SDRAM_OFFSET(x) 0x4##x
74 #define CONFIG_SYS_SDRAM_BASE 0x40000000
75 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
76 /* V3s do not have enough memory to place code at 0x4a000000 */
78 #define CONFIG_SYS_TEXT_BASE 0x4a000000
80 #define CONFIG_SYS_TEXT_BASE 0x42e00000
85 #define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
86 #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
89 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
93 * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
95 * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
96 * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
97 * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
99 #define CONFIG_SYS_INIT_RAM_ADDR 0x10000
100 #define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
102 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
103 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
113 #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
139 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
144 #define CONFIG_MMC_SUNXI_SLOT 0
148 #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
182 #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
183 #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
186 #define LOW_LEVEL_SRAM_STACK 0x00054000
188 #define LOW_LEVEL_SRAM_STACK 0x00018000
191 #define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
192 #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
193 #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
213 #define CONFIG_SYS_I2C_SLAVE 0x7f
220 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
228 #define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
231 #define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
332 #define BOOTM_SIZE __stringify(0xa000000)
346 #define BOOTM_SIZE __stringify(0xa000000)
358 #define BOOTM_SIZE __stringify(0x2e00000)
368 "bootm_size=" BOOTM_SIZE "\0" \
369 "kernel_addr_r=" KERNEL_ADDR_R "\0" \
370 "fdt_addr_r=" FDT_ADDR_R "\0" \
371 "scriptaddr=" SCRIPT_ADDR_R "\0" \
372 "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
373 "ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
377 "kernel ram " KERNEL_ADDR_R " 0x1000000;" \
378 "fdt ram " FDT_ADDR_R " 0x100000;" \
379 "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
382 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
394 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
400 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
411 "fi\0"
428 "if ext2load mmc 0 0x44000000 uEnv.txt; then " \
430 "env import -t 0x44000000 ${filesize}; " \
433 "ext2load mmc 0 0x43000000 script.bin && " \
434 "ext2load mmc 0 0x48000000 uImage && " \
435 "bootm 0x48000000\0"
444 "preboot=usb start\0" \
445 "stdin=serial,usbkbd\0"
448 "stdin=serial\0"
453 "stdout=serial,vga\0" \
454 "stderr=serial,vga\0"
458 "stdout=serial,vidconsole\0" \
459 "stderr=serial,vidconsole\0"
462 "stdout=serial\0" \
463 "stderr=serial\0"
468 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"
475 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
494 "fdtfile=" FDTFILE "\0" \
495 "console=ttyS0,115200\0" \