Lines Matching +full:0 +full:x8000c000
28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
92 #define CONFIG_SYS_TEXT_BASE 0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
100 #define CONFIG_SYS_TEXT_BASE 0x11000000
101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
105 #define CONFIG_SYS_TEXT_BASE 0xeff80000
107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
142 #define CONFIG_SYS_CCSRBAR 0xffe00000
163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
169 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
170 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
171 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
172 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
173 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
174 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
176 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
177 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
178 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
179 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
181 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
182 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
183 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
184 #define CONFIG_SYS_DDR_RCW_1 0x00000000
185 #define CONFIG_SYS_DDR_RCW_2 0x00000000
187 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
189 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
191 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
192 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
193 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
195 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
196 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
197 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
198 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
199 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
200 #define CONFIG_SYS_DDR_MODE_1 0x40461520
201 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
202 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
209 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
210 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
211 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
212 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
214 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
215 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
216 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
223 #define CONFIG_SYS_FLASH_BASE 0xec000000
230 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
250 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
256 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
265 #define CONFIG_SYS_PMC_BASE 0xff980000
288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
306 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
307 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
308 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
313 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
314 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
315 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
316 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
329 * Memory space is mapped 1-1, but I/O space must start from 0.
334 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
335 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
336 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
337 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
338 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
339 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
340 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
341 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
345 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
346 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
347 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
348 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
349 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
350 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
351 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
352 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
362 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
363 #define CONFIG_ENV_SIZE 0x20000
364 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
368 #define CONFIG_ENV_SPI_BUS 0
369 #define CONFIG_ENV_SPI_CS 0
371 #define CONFIG_ENV_SPI_MODE 0
375 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
376 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
377 #define CONFIG_ENV_SECT_SIZE 0x1000
387 #define CONFIG_ENV_SIZE 0x2000
388 #define CONFIG_SYS_MMC_ENV_DEV 0
391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
392 #define CONFIG_ENV_SIZE 0x2000
396 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
398 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
442 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
477 #define TSEC2_PHY_ADDR 0
478 #define TSEC2_PHY_ADDR_SGMII 0x00
485 #define TSEC1_PHYIDX 0
486 #define TSEC2_PHYIDX 0
487 #define TSEC3_PHYIDX 0
502 "bootcmd=run prog_spi_mbrbootcramfs\0" \
503 "bootfile=uImage\0" \
504 "consoledev=ttyS0\0" \
505 "cramfsfile=image.cramfs\0" \
506 "dtbaddr=0x00c00000\0" \
507 "dtbfile=image.dtb\0" \
508 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
509 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
510 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
511 "fileaddr=0x01000000\0" \
512 "filesize=0x00080000\0" \
513 "flashmbr=sf probe 0; " \
516 "sf write $loadaddr $mbr_offset $filesize\0" \
521 "protect on $nor_recoveryaddr +$filesize\0 " \
526 "protect on $nor_ubootaddr +$filesize\0 " \
531 "protect on $nor_workingaddr +$filesize\0 " \
532 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
533 "kerneladdr=0x01100000\0" \
534 "kernelfile=uImage\0" \
535 "loadaddr=0x01000000\0" \
536 "mbr=uCP1020d.mbr\0" \
537 "mbr_offset=0x00000000\0" \
538 "mmbr=uCP1020Quiet.mbr\0" \
539 "mmcpart=0:2\0" \
542 "mmc write $loadaddr 1 1\0" \
544 "mmc erase 0x40 0x400; " \
545 "mmc write $loadaddr 0x40 0x400\0" \
546 "netdev=eth0\0" \
547 "nor_recoveryaddr=0xEC0A0000\0" \
548 "nor_ubootaddr=0xEFF80000\0" \
549 "nor_workingaddr=0xECFA0000\0" \
553 "bootm $kerneladdr - $dtbaddr\0" \
557 "bootm $kerneladdr - $dtbaddr\0" \
558 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
561 "cramfsload $kerneladdr $kernelfile\0" \
562 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
565 "cramfsload $kerneladdr $kernelfile\0" \
566 "prog_spi_mbr=run spi__mbr\0" \
567 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
569 "run spi__cramfs\0" \
575 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
576 "ramdisk_size=120000\0" \
577 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
578 "recoveryaddr=0x02F00000\0" \
579 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
580 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
581 "mw.l 0xffe0f008 0x00400000\0" \
582 "rootfsaddr=0x02F00000\0" \
583 "rootfsfile=rootfs.ext2.gz.uboot\0" \
584 "rootpath=/opt/nfsroot\0" \
586 "protect off 0xeC000000 +$filesize; " \
587 "erase 0xEC000000 +$filesize; " \
588 "cp.b $loadaddr 0xEC000000 $filesize; " \
589 "cmp.b $loadaddr 0xEC000000 $filesize; " \
590 "protect on 0xeC000000 +$filesize\0" \
592 "protect off 0xeFF80000 +$filesize; " \
593 "erase 0xEFF80000 +$filesize; " \
594 "cp.b $loadaddr 0xEFF80000 $filesize; " \
595 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
596 "protect on 0xeFF80000 +$filesize\0" \
598 "sf probe 0; sf erase 0x8000 +$filesize; " \
599 "sf write $loadaddr 0x8000 $filesize\0" \
601 "protect off 0xec0a0000 +$filesize; " \
602 "erase 0xeC0A0000 +$filesize; " \
603 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
604 "protect on 0xec0a0000 +$filesize\0" \
606 "sf probe 1; sf erase 0 +$filesize; " \
607 "sf write $loadaddr 0 $filesize\0" \
609 "sf probe 0; sf erase 0 +$filesize; " \
610 "sf write $loadaddr 0 $filesize\0" \
616 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
617 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
618 "ubootaddr=0x01000000\0" \
619 "ubootfile=u-boot.bin\0" \
620 "ubootd=u-boot4dongle.bin\0" \
621 "upgrade=run flashworking\0" \
622 "usb_phy_type=ulpi\0 " \
623 "workingaddr=0x02F00000\0" \
624 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
631 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
632 "bootfile=uImage\0" \
633 "consoledev=ttyS0\0" \
634 "cramfsfile=image.cramfs\0" \
635 "dtbaddr=0x00c00000\0" \
636 "dtbfile=image.dtb\0" \
637 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
638 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
639 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
640 "fileaddr=0x01000000\0" \
641 "filesize=0x00080000\0" \
642 "flashmbr=sf probe 0; " \
645 "sf write $loadaddr $mbr_offset $filesize\0" \
650 "protect on $nor_recoveryaddr +$filesize\0 " \
655 "protect on $nor_ubootaddr +$filesize\0 " \
660 "protect on $nor_workingaddr +$filesize\0 " \
661 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
662 "kerneladdr=0x01100000\0" \
663 "kernelfile=uImage\0" \
664 "loadaddr=0x01000000\0" \
665 "mbr=uCP1020.mbr\0" \
666 "mbr_offset=0x00000000\0" \
667 "netdev=eth0\0" \
668 "nor_recoveryaddr=0xEC0A0000\0" \
669 "nor_ubootaddr=0xEFF80000\0" \
670 "nor_workingaddr=0xECFA0000\0" \
674 "bootm $kerneladdr - $dtbaddr\0" \
678 "bootm $kerneladdr - $dtbaddr\0" \
679 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
682 "cramfsload $kerneladdr $kernelfile\0" \
683 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
686 "cramfsload $kerneladdr $kernelfile\0" \
687 "othbootargs=quiet\0" \
693 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
694 "ramdisk_size=120000\0" \
695 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
696 "recoveryaddr=0x02F00000\0" \
697 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
698 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
699 "mw.l 0xffe0f008 0x00400000\0" \
700 "rootfsaddr=0x02F00000\0" \
701 "rootfsfile=rootfs.ext2.gz.uboot\0" \
702 "rootpath=/opt/nfsroot\0" \
703 "silent=1\0" \
709 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
710 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
711 "ubootaddr=0x01000000\0" \
712 "ubootfile=u-boot.bin\0" \
713 "upgrade=run flashworking\0" \
714 "workingaddr=0x02F00000\0" \
715 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
720 "bootcmd=run norkernel\0" \
721 "bootfile=uImage\0" \
722 "consoledev=ttyS0\0" \
723 "dtbaddr=0x00c00000\0" \
724 "dtbfile=image.dtb\0" \
725 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
726 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
727 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
728 "fileaddr=0x01000000\0" \
729 "filesize=0x00080000\0" \
730 "flashmbr=sf probe 0; " \
733 "sf write $loadaddr $mbr_offset $filesize\0" \
742 "protect on $nor_ubootaddr1 +$filesize\0 " \
744 "erase $part0base +$part0size\0" \
746 "erase $part1base +$part1size\0" \
748 "erase $part2base +$part2size\0" \
750 "erase $part3base +$part3size\0" \
751 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
752 "kerneladdr=0x01100000\0" \
753 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
754 "kernelfile=uImage\0" \
755 "loadaddr=0x01000000\0" \
756 "mbr=uCP1020.mbr\0" \
757 "mbr_offset=0x00000000\0" \
758 "netdev=eth0\0" \
759 "nor_ubootaddr0=0xEC000000\0" \
760 "nor_ubootaddr1=0xEFF80000\0" \
763 "bootm $kerneladdr - $dtbaddr\0" \
764 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
767 "cramfsload $kerneladdr $kernelfile\0" \
768 "part0base=0xEC100000\0" \
769 "part0size=0x00700000\0" \
770 "part1base=0xEC800000\0" \
771 "part1size=0x02000000\0" \
772 "part2base=0xEE800000\0" \
773 "part2size=0x00800000\0" \
774 "part3base=0xEF000000\0" \
775 "part3size=0x00F80000\0" \
776 "partENVbase=0xEC080000\0" \
777 "partENVsize=0x00080000\0" \
783 "cmp.b $loadaddr $part0base $filesize\0" \
789 "cmp.b $loadaddr $part1base $filesize\0" \
795 "cmp.b $loadaddr $part2base $filesize\0" \
801 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
802 "ramdisk_size=120000\0" \
803 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
804 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
805 "mw.l 0xffe0f008 0x00400000\0" \
806 "rootfsaddr=0x02F00000\0" \
807 "rootfsfile=rootfs.ext2.gz.uboot\0" \
808 "rootpath=/opt/nfsroot\0" \
810 "sf probe 0; sf erase 0 +$filesize; " \
811 "sf write $loadaddr 0 $filesize\0" \
813 "protect off 0xeC000000 +$filesize; " \
814 "erase 0xEC000000 +$filesize; " \
815 "cp.b $loadaddr 0xEC000000 $filesize; " \
816 "cmp.b $loadaddr 0xEC000000 $filesize; " \
817 "protect on 0xeC000000 +$filesize\0" \
823 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
824 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
825 "ubootfile=u-boot.bin\0" \
826 "upgrade=run flashuboot\0" \
827 "usb_phy_type=ulpi\0 " \
835 "bootm $loadaddr - $fdtaddr\0" \
840 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
841 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
842 "bootm $loadaddr - $fdtaddr\0" \
848 "fatload usb 0:2 $loadaddr $bootfile;" \
849 "fatload usb 0:2 $fdtaddr $fdtfile;" \
850 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
851 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
857 "ext2load usb 0:4 $loadaddr $bootfile;" \
858 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
859 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
860 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
864 "bootm $norbootaddr - $norfdtaddr\0 " \
872 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"