Lines Matching +full:0 +full:xfdd00000
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SYS_TEXT_BASE 0x00201000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #define RESET_VECTOR_OFFSET 0x27FFC
31 #define BOOT_PAGE_OFFSET 0x27000
34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
64 #define CONFIG_SYS_TEXT_BASE 0xeff40000
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_END 0x00400000
103 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
114 #define CONFIG_SYS_DCSRBAR 0xf0000000
115 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
121 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
133 #define CONFIG_SYS_FLASH_BASE 0xe0000000
134 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
150 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
151 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
157 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
173 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
180 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
181 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
186 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
188 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
189 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
193 * Memory space is mapped 1-1, but I/O space must start from 0.
197 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
198 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
199 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
200 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
201 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
202 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
203 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
204 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
208 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
209 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
210 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
211 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
212 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
213 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
214 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
217 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
218 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
219 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
220 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
221 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
222 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
223 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
224 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
227 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
228 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
229 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
230 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
231 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
232 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
277 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
302 "setenv bootargs config-addr=0x60000000; " \
303 "bootm 0x01000000 - 0x00f00000"
314 #define CONFIG_ENV_SPI_BUS 0
315 #define CONFIG_ENV_SPI_CS 0
317 #define CONFIG_ENV_SPI_MODE 0
318 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
319 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
320 #define CONFIG_ENV_SECT_SIZE 0x10000
323 #define CONFIG_SYS_MMC_ENV_DEV 0
324 #define CONFIG_ENV_SIZE 0x2000
325 #define CONFIG_ENV_OFFSET (512 * 0x800)
331 #define CONFIG_ENV_SIZE 0x2000
334 #define CONFIG_ENV_SIZE 0x2000
335 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
349 #define CONFIG_SYS_SPD_BUS_NUM 0
350 #define SPD_EEPROM_ADDRESS1 0x52
351 #define SPD_EEPROM_ADDRESS2 0x54
352 #define SPD_EEPROM_ADDRESS3 0x56
359 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
361 + 0x8000000) | \
365 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
374 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
375 FTIM0_NOR_TEADC(0x5) | \
376 FTIM0_NOR_TEAHC(0x5))
377 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
378 FTIM1_NOR_TRAD_NOR(0x1A) |\
379 FTIM1_NOR_TSEQRAD_NOR(0x13))
380 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
381 FTIM2_NOR_TCH(0x4) | \
382 FTIM2_NOR_TWPH(0x0E) | \
383 FTIM2_NOR_TWP(0x1c))
384 #define CONFIG_SYS_NOR_FTIM3 0x0
396 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
402 #define CONFIG_SYS_NAND_BASE 0xff800000
403 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
405 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
423 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
424 FTIM0_NAND_TWP(0x18) | \
425 FTIM0_NAND_TWCHT(0x07) | \
426 FTIM0_NAND_TWH(0x0a))
427 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
428 FTIM1_NAND_TWBE(0x39) | \
429 FTIM1_NAND_TRR(0x0e) | \
430 FTIM1_NAND_TRP(0x18))
431 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
432 FTIM2_NAND_TREH(0x0a) | \
433 FTIM2_NAND_TWHRE(0x1e))
434 #define CONFIG_SYS_NAND_FTIM3 0x0
487 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
488 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
489 #define CONFIG_SYS_CSPR3_EXT (0xf)
496 #define CONFIG_SYS_CSOR3 0x0
499 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
500 FTIM0_GPCM_TEADC(0x0e) | \
501 FTIM0_GPCM_TEAHC(0x0e))
502 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
503 FTIM1_GPCM_TRAD(0x1f))
504 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
505 FTIM2_GPCM_TCH(0x8) | \
506 FTIM2_GPCM_TWP(0x1f))
507 #define CONFIG_SYS_CS3_FTIM3 0x0
516 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
517 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
519 #define I2C_MUX_CH_DEFAULT 0x8
520 #define I2C_MUX_CH_VOL_MONITOR 0xa
521 #define I2C_MUX_CH_VSC3316_FS 0xc
522 #define I2C_MUX_CH_VSC3316_BS 0xd
525 #define I2C_VOL_MONITOR_ADDR 0x40
526 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
527 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
544 #define CONFIG_SF_DEFAULT_MODE 0
550 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
551 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
552 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
553 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
554 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
560 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
562 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
563 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
564 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
565 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
566 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
572 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
584 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
585 * env, so we got 0x110000.
588 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
591 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
593 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
596 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
602 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
604 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
605 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
614 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
615 #define CONFIG_CORTINA_FW_LENGTH 0x40000
617 #define SGMII_PHY_ADDR1 0x0
618 #define SGMII_PHY_ADDR2 0x1
619 #define SGMII_PHY_ADDR3 0x2
620 #define SGMII_PHY_ADDR4 0x3
621 #define SGMII_PHY_ADDR5 0x4
622 #define SGMII_PHY_ADDR6 0x5
623 #define SGMII_PHY_ADDR7 0x6
624 #define SGMII_PHY_ADDR8 0x7
625 #define FM1_10GEC1_PHY_ADDR 0x10
626 #define FM1_10GEC2_PHY_ADDR 0x11
627 #define FM2_10GEC1_PHY_ADDR 0x12
628 #define FM2_10GEC2_PHY_ADDR 0x13
689 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
690 "netdev=eth0\0" \
691 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
692 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
698 "cmp.b $loadaddr $ubootaddr $filesize\0" \
699 "consoledev=ttyS0\0" \
700 "ramdiskaddr=2000000\0" \
701 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
702 "fdtaddr=1e00000\0" \
703 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
704 "bdev=sda3\0"
707 "setenv bootargs config-addr=0x60000000; " \
708 "bootm 0x01000000 - 0x00f00000"
713 "setenv ramdiskaddr 0x02000000;" \
714 "setenv fdtaddr 0x00c00000;" \
715 "setenv loadaddr 0x1000000;" \