Lines Matching +full:0 +full:xe2800000
31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
34 #define CONFIG_SPL_PAD_TO 0x4000
37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
50 #define CONFIG_SYS_TEXT_BASE 0xFE000000
83 #define CONFIG_SYS_IMMR 0xE0000000
89 #define CONFIG_SYS_MEMTEST_START 0x00001000
90 #define CONFIG_SYS_MEMTEST_END 0x07f00000
98 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
99 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
112 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
120 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
134 /* 0x80010102 */
136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
138 | (0 << TIMING_CFG0_WRT_SHIFT) \
139 | (0 << TIMING_CFG0_RRT_SHIFT) \
140 | (0 << TIMING_CFG0_WWT_SHIFT) \
145 /* 0x00220802 */
154 /* 0x3835a322 */
162 /* 0x129048c6 */ /* P9-45,may need tuning */
165 /* 0x05100500 */
171 /* 0x43088000 */
176 /* 0x43080000 */
178 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
180 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
181 | (0x0632 << SDRAM_MODE_SD_SHIFT))
182 /* 0x44480632 */
183 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
186 /*0x02000000*/
197 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
212 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
230 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
231 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
246 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
247 | (0xFF << LBCR_BMT_SHIFT) \
248 | 0xF) /* 0x0004ff0f */
251 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
255 #define CONFIG_SYS_NAND_BASE 0xFFF00000
257 #define CONFIG_SYS_NAND_BASE 0xE2800000
283 /* 0xFFFF8396 */
304 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
305 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
306 /* map at 0xFA000000 on LCS3 */
311 /* 0xFA000801 */
320 /* 0xFFFF8FF7 */
329 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
330 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
344 /* 0xFFFE09FF */
364 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
365 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
371 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
372 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
374 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
375 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
376 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
382 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
384 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
385 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
387 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
388 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
389 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
390 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
392 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
404 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
405 #define TSEC1_PHY_ADDR 0x1c
407 #define TSEC1_PHYIDX 0
413 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
416 #define TSEC2_PHYIDX 0
419 /* Options are: TSEC[0-1] */
426 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
442 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
443 #define CONFIG_ENV_SIZE 0x2000
447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
448 #define CONFIG_ENV_SIZE 0x2000
473 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
488 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
493 /* 0x62040000 */
495 0x20000000 /* reserved, must be set */ |\
507 /* 0x65040000 */
509 0x20000000 /* reserved, must be set */ |\
547 #define CONFIG_SYS_HID0_INIT 0x000000000
556 /* DDR @ 0x00000000 */
563 /* PCI @ 0x80000000 */
579 #define CONFIG_SYS_IBAT3L (0)
580 #define CONFIG_SYS_IBAT3U (0)
581 #define CONFIG_SYS_IBAT4L (0)
582 #define CONFIG_SYS_IBAT4U (0)
584 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
594 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
595 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
596 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
598 #define CONFIG_SYS_IBAT7L (0)
599 #define CONFIG_SYS_IBAT7U (0)
636 "netdev=" CONFIG_NETDEV "\0" \
637 "ethprime=TSEC1\0" \
638 "uboot=" CONFIG_UBOOTPATH "\0" \
649 " $filesize\0" \
650 "fdtaddr=780000\0" \
651 "fdtfile=" CONFIG_FDTFILE "\0" \
652 "console=ttyS0\0" \
654 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
658 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"