77 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,  in anx6345_write_r0()  function
167 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);  in anx6345_aux_addr()
169 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);  in anx6345_aux_addr()
171 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);  in anx6345_aux_addr()
191 			anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);  in anx6345_aux_transfer()
195 	anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);  in anx6345_aux_transfer()
196 	anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);  in anx6345_aux_transfer()
314 		anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);  in anx6345_init()
325 	anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);  in anx6345_init()
327 	anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);  in anx6345_init()
330 	anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,  in anx6345_init()
334 	anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);  in anx6345_init()
335 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);  in anx6345_init()
336 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);  in anx6345_init()
337 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);  in anx6345_init()
338 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);  in anx6345_init()
347 	anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);  in anx6345_init()
348 	anx6345_write_r0(dev, 0xa7, 0x00);  in anx6345_init()
385 	anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);  in anx6345_enable()
386 	anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);  in anx6345_enable()
389 	anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,  in anx6345_enable()
408 	anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,  in anx6345_enable()