1 /*
2 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <i2c.h>
11 #include <edid.h>
12 #include <video_bridge.h>
13 #include "../anx98xx-edp.h"
14 #include "../drm/rockchip_bridge.h"
15
16 #define DP_MAX_LINK_RATE 0x001
17 #define DP_MAX_LANE_COUNT 0x002
18 #define DP_MAX_LANE_COUNT_MASK 0x1f
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 struct anx6345_priv {
23 u8 chipid;
24 u8 edid[EDID_SIZE];
25 };
26
anx6345_write(struct udevice * dev,unsigned int addr_off,unsigned char reg_addr,unsigned char value)27 static int anx6345_write(struct udevice *dev, unsigned int addr_off,
28 unsigned char reg_addr, unsigned char value)
29 {
30 uint8_t buf[2];
31 struct i2c_msg msg;
32 int ret;
33
34 msg.addr = addr_off;
35 msg.flags = 0;
36 buf[0] = reg_addr;
37 buf[1] = value;
38 msg.buf = buf;
39 msg.len = 2;
40 ret = dm_i2c_xfer(dev, &msg, 1);
41 if (ret) {
42 debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
43 __func__, reg_addr, value, ret);
44 return ret;
45 }
46
47 return 0;
48 }
49
anx6345_read(struct udevice * dev,unsigned int addr_off,unsigned char reg_addr,unsigned char * value)50 static int anx6345_read(struct udevice *dev, unsigned int addr_off,
51 unsigned char reg_addr, unsigned char *value)
52 {
53 uint8_t addr, val;
54 struct i2c_msg msg[2];
55 int ret;
56
57 msg[0].addr = addr_off;
58 msg[0].flags = 0;
59 addr = reg_addr;
60 msg[0].buf = &addr;
61 msg[0].len = 1;
62 msg[1].addr = addr_off;
63 msg[1].flags = I2C_M_RD;
64 msg[1].buf = &val;
65 msg[1].len = 1;
66 ret = dm_i2c_xfer(dev, msg, 2);
67 if (ret) {
68 debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
69 __func__, (int)reg_addr, value, ret);
70 return ret;
71 }
72 *value = val;
73
74 return 0;
75 }
76
anx6345_write_r0(struct udevice * dev,unsigned char reg_addr,unsigned char value)77 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
78 unsigned char value)
79 {
80 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
81
82 return anx6345_write(dev, chip->chip_addr, reg_addr, value);
83 }
84
anx6345_read_r0(struct udevice * dev,unsigned char reg_addr,unsigned char * value)85 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
86 unsigned char *value)
87 {
88 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
89
90 return anx6345_read(dev, chip->chip_addr, reg_addr, value);
91 }
92
anx6345_write_r1(struct udevice * dev,unsigned char reg_addr,unsigned char value)93 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
94 unsigned char value)
95 {
96 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
97
98 return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
99 }
100
anx6345_read_r1(struct udevice * dev,unsigned char reg_addr,unsigned char * value)101 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
102 unsigned char *value)
103 {
104 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
105
106 return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
107 }
108
anx6345_set_backlight(struct udevice * dev,int percent)109 static int anx6345_set_backlight(struct udevice *dev, int percent)
110 {
111 return -ENOSYS;
112 }
113
anx6345_aux_wait(struct udevice * dev)114 static int anx6345_aux_wait(struct udevice *dev)
115 {
116 int ret = -ETIMEDOUT;
117 u8 v;
118 int retries = 1000;
119
120 do {
121 anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
122 if (!(v & ANX9804_AUX_EN)) {
123 ret = 0;
124 break;
125 }
126 udelay(100);
127 } while (retries--);
128
129 if (ret) {
130 debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
131 return ret;
132 }
133
134 ret = -ETIMEDOUT;
135 retries = 1000;
136 do {
137 anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
138 if (v & ANX9804_RPLY_RECEIV) {
139 ret = 0;
140 break;
141 }
142 udelay(100);
143 } while (retries--);
144
145 if (ret) {
146 debug("%s: timed out waiting to receive reply\n", __func__);
147 return ret;
148 }
149
150 /* Clear RPLY_RECEIV bit */
151 anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
152
153 anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
154 if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
155 debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
156 ret = -EIO;
157 }
158
159 return ret;
160 }
161
anx6345_aux_addr(struct udevice * dev,u32 addr)162 static void anx6345_aux_addr(struct udevice *dev, u32 addr)
163 {
164 u8 val;
165
166 val = addr & 0xff;
167 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
168 val = (addr >> 8) & 0xff;
169 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
170 val = (addr >> 16) & 0x0f;
171 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
172 }
173
anx6345_aux_transfer(struct udevice * dev,u8 req,u32 addr,u8 * buf,size_t len)174 static int anx6345_aux_transfer(struct udevice *dev, u8 req,
175 u32 addr, u8 *buf, size_t len)
176 {
177 int i, ret;
178 u8 ctrl1 = req;
179 u8 ctrl2 = ANX9804_AUX_EN;
180
181 if (len > 16)
182 return -E2BIG;
183
184 if (len)
185 ctrl1 |= ANX9804_AUX_LENGTH(len);
186 else
187 ctrl2 |= ANX9804_ADDR_ONLY;
188
189 if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
190 for (i = 0; i < len; i++)
191 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
192 }
193
194 anx6345_aux_addr(dev, addr);
195 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
196 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
197 ret = anx6345_aux_wait(dev);
198 if (ret) {
199 debug("AUX transaction timed out\n");
200 return ret;
201 }
202
203 if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
204 for (i = 0; i < len; i++)
205 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
206 }
207
208 return 0;
209 }
210
anx6345_read_aux_i2c(struct udevice * dev,u8 chip_addr,u8 offset,size_t count,u8 * buf)211 static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
212 u8 offset, size_t count, u8 *buf)
213 {
214 int i, ret;
215 size_t cur_cnt;
216 u8 cur_offset;
217
218 for (i = 0; i < count; i += 16) {
219 cur_cnt = (count - i) > 16 ? 16 : count - i;
220 cur_offset = offset + i;
221 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
222 chip_addr, &cur_offset, 1);
223 if (ret) {
224 debug("%s: failed to set i2c offset: %d\n",
225 __func__, ret);
226 return ret;
227 }
228 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
229 chip_addr, buf + i, cur_cnt);
230 if (ret) {
231 debug("%s: failed to read from i2c device: %d\n",
232 __func__, ret);
233 return ret;
234 }
235 }
236
237 return 0;
238 }
239
anx6345_read_dpcd(struct udevice * dev,u32 reg,u8 * val)240 static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
241 {
242 int ret;
243
244 ret = anx6345_aux_transfer(dev,
245 ANX9804_AUX_TX_COMM_READ |
246 ANX9804_AUX_TX_COMM_DP_TRANSACTION,
247 reg, val, 1);
248 if (ret) {
249 debug("Failed to read DPCD\n");
250 return ret;
251 }
252
253 return 0;
254 }
255
anx6345_read_edid(struct udevice * dev,u8 * buf,int size)256 static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
257 {
258 struct anx6345_priv *priv = dev_get_priv(dev);
259 int ret;
260
261 ret = anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
262 if (ret < 0) {
263 dev_err(dev, "failed to get edid\n");
264 return ret;
265 }
266
267 if (size > EDID_SIZE)
268 size = EDID_SIZE;
269 memcpy(buf, priv->edid, size);
270
271 return size;
272 }
273
anx6345_attach(struct udevice * dev)274 static int anx6345_attach(struct udevice *dev)
275 {
276 /* No-op */
277 return 0;
278 }
279
anx6345_init(struct udevice * dev)280 static int anx6345_init(struct udevice *dev)
281 {
282 struct anx6345_priv *priv = dev_get_priv(dev);
283 u8 c;
284 int ret, i;
285
286 /* Deassert reset and enable power */
287 ret = video_bridge_set_active(dev, true);
288 if (ret)
289 return ret;
290
291 /* Reset */
292 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
293 mdelay(100);
294 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
295
296 /* Write 0 to the powerdown reg (powerup everything) */
297 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
298
299 ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &priv->chipid);
300 if (ret)
301 debug("%s: read id failed: %d\n", __func__, ret);
302
303 switch (priv->chipid) {
304 case 0x63:
305 debug("ANX63xx detected.\n");
306 break;
307 default:
308 debug("Error anx6345 chipid mismatch: %.2x\n", priv->chipid);
309 return -ENODEV;
310 }
311
312 for (i = 0; i < 100; i++) {
313 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
314 anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
315 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
316 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
317 break;
318
319 mdelay(5);
320 }
321 if (i == 100)
322 debug("Error anx6345 clock is not stable\n");
323
324 /* Set a bunch of analog related register values */
325 anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
326 anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
327 anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
328
329 /* Force HPD */
330 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
331 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
332
333 /* Power up and configure lanes */
334 anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
335 anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
336 anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
337 anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
338 anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
339
340 /* Reset AUX CH */
341 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
342 ANX9804_RST_CTRL2_AUX);
343 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
344
345 /* Powerdown audio and some other unused bits */
346 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
347 anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
348 anx6345_write_r0(dev, 0xa7, 0x00);
349
350 return 0;
351 }
352
anx6345_enable(struct udevice * dev)353 static int anx6345_enable(struct udevice *dev)
354 {
355 u8 colordepth, lanes, data_rate, c;
356 int i, bpp;
357 struct display_timing timing;
358 struct anx6345_priv *priv = dev_get_priv(dev);
359
360 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
361 debug("Failed to parse EDID\n");
362 return -EIO;
363 }
364 debug("%s: panel found: %dx%d, bpp %d\n", __func__,
365 timing.hactive.typ, timing.vactive.typ, bpp);
366 if (bpp == 6)
367 colordepth = 0x00; /* 6 bit */
368 else
369 colordepth = 0x10; /* 8 bit */
370 anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
371
372 if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
373 debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
374 return -EIO;
375 }
376 debug("%s: data_rate: %d\n", __func__, (int)data_rate);
377 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
378 debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
379 return -EIO;
380 }
381 lanes &= DP_MAX_LANE_COUNT_MASK;
382 debug("%s: lanes: %d\n", __func__, (int)lanes);
383
384 /* Set data-rate / lanes */
385 anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
386 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
387
388 /* Link training */
389 anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
390 ANX9804_LINK_TRAINING_CTRL_EN);
391 mdelay(5);
392 for (i = 0; i < 100; i++) {
393 anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
394 if ((priv->chipid == 0x63) && (c & 0x80) == 0)
395 break;
396
397 mdelay(5);
398 }
399 if (i == 100) {
400 debug("Error anx6345 link training timeout\n");
401 return -ENODEV;
402 }
403
404 /* Enable */
405 anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG, ANX9804_VID_CTRL1_VID_EN |
406 ANX9804_VID_CTRL1_DDR_CTRL | ANX9804_VID_CTRL1_EDGE);
407 /* Force stream valid */
408 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
409 ANX9804_SYS_CTRL3_F_HPD |
410 ANX9804_SYS_CTRL3_HPD_CTRL |
411 ANX9804_SYS_CTRL3_F_VALID |
412 ANX9804_SYS_CTRL3_VALID_CTRL);
413
414 return 0;
415 }
416
anx6345_probe(struct udevice * dev)417 static int anx6345_probe(struct udevice *dev)
418 {
419 struct rockchip_bridge *bridge =
420 (struct rockchip_bridge *)dev_get_driver_data(dev);
421
422 if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
423 return -EPROTONOSUPPORT;
424
425 bridge->dev = dev;
426
427 return anx6345_init(dev);
428 }
429
430 static const struct video_bridge_ops anx6345_ops = {
431 .attach = anx6345_attach,
432 .set_backlight = anx6345_set_backlight,
433 .read_edid = anx6345_read_edid,
434 };
435
anx6345_bridge_enable(struct rockchip_bridge * bridge)436 static void anx6345_bridge_enable(struct rockchip_bridge *bridge)
437 {
438 anx6345_enable(bridge->dev);
439 }
440
441 static const struct rockchip_bridge_funcs anx6345_bridge_funcs = {
442 .enable = anx6345_bridge_enable,
443 };
444
445 static struct rockchip_bridge anx6345_driver_data = {
446 .funcs = &anx6345_bridge_funcs,
447 };
448
449 static const struct udevice_id anx6345_ids[] = {
450 {
451 .compatible = "analogix,anx6345",
452 .data = (ulong)&anx6345_driver_data, },
453 { }
454 };
455
456 U_BOOT_DRIVER(analogix_anx6345) = {
457 .name = "analogix_anx6345",
458 .id = UCLASS_VIDEO_BRIDGE,
459 .of_match = anx6345_ids,
460 .probe = anx6345_probe,
461 .ops = &anx6345_ops,
462 .priv_auto_alloc_size = sizeof(struct anx6345_priv),
463 };
464