Lines Matching refs:usbcfg

331 	uint32_t usbcfg = 0;  in dwc_otg_core_init()  local
335 usbcfg = readl(&regs->gusbcfg); in dwc_otg_core_init()
339 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; in dwc_otg_core_init()
341 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | in dwc_otg_core_init()
345 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; in dwc_otg_core_init()
350 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; in dwc_otg_core_init()
352 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; in dwc_otg_core_init()
354 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
398 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); in dwc_otg_core_init()
399 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; in dwc_otg_core_init()
401 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ in dwc_otg_core_init()
403 usbcfg |= DWC2_GUSBCFG_DDRSEL; in dwc_otg_core_init()
405 usbcfg &= ~DWC2_GUSBCFG_DDRSEL; in dwc_otg_core_init()
409 usbcfg |= DWC2_GUSBCFG_PHYIF; in dwc_otg_core_init()
413 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
419 usbcfg = readl(&regs->gusbcfg); in dwc_otg_core_init()
420 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); in dwc_otg_core_init()
428 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; in dwc_otg_core_init()
429 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; in dwc_otg_core_init()
433 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; in dwc_otg_core_init()
435 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
464 usbcfg = 0; in dwc_otg_core_init()
467 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; in dwc_otg_core_init()
469 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; in dwc_otg_core_init()
472 setbits_le32(&regs->gusbcfg, usbcfg); in dwc_otg_core_init()