1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-rockchip.h"
16 		/* pwm0-0 */
21 		.route_val = BIT(16),
23 		/* pwm0-1 */
28 		.route_val = BIT(16) | BIT(0),
30 		/* pwm1-0 */
35 		.route_val = BIT(16 + 1),
37 		/* pwm1-1 */
42 		.route_val = BIT(16 + 1) | BIT(1),
44 		/* pwm2-0 */
49 		.route_val = BIT(16 + 2),
51 		/* pwm2-1 */
56 		.route_val = BIT(16 + 2) | BIT(2),
58 		/* pwm3-0 */
63 		.route_val = BIT(16 + 3),
65 		/* pwm3-1 */
70 		.route_val = BIT(16 + 3) | BIT(3),
72 		/* sdio-0_d0 */
77 		.route_val = BIT(16 + 4),
79 		/* sdio-1_d0 */
84 		.route_val = BIT(16 + 4) | BIT(4),
86 		/* spi-0_rx */
91 		.route_val = BIT(16 + 5),
93 		/* spi-1_rx */
98 		.route_val = BIT(16 + 5) | BIT(5),
100 		/* emmc-0_cmd */
105 		.route_val = BIT(16 + 7),
107 		/* emmc-1_cmd */
112 		.route_val = BIT(16 + 7) | BIT(7),
114 		/* uart2-0_rx */
119 		.route_val = BIT(16 + 8),
121 		/* uart2-1_rx */
126 		.route_val = BIT(16 + 8) | BIT(8),
128 		/* uart1-0_rx */
133 		.route_val = BIT(16 + 11),
135 		/* uart1-1_rx */
140 		.route_val = BIT(16 + 11) | BIT(11),
146 	struct rockchip_pinctrl_priv *priv = bank->priv;  in rk3228_set_mux()
150 	u8 bit;  in rk3228_set_mux()  local
153 	regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)  in rk3228_set_mux()
154 				? priv->regmap_pmu : priv->regmap_base;  in rk3228_set_mux()
157 	mux_type = bank->iomux[iomux_num].type;  in rk3228_set_mux()
158 	reg = bank->iomux[iomux_num].offset;  in rk3228_set_mux()
159 	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);  in rk3228_set_mux()
161 	data = (mask << (bit + 16));  in rk3228_set_mux()
162 	data |= (mux & mask) << bit;  in rk3228_set_mux()
172 					 int *reg, u8 *bit)  in rk3228_calc_pull_reg_and_bit()  argument
174 	struct rockchip_pinctrl_priv *priv = bank->priv;  in rk3228_calc_pull_reg_and_bit()
176 	*regmap = priv->regmap_base;  in rk3228_calc_pull_reg_and_bit()
178 	*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;  in rk3228_calc_pull_reg_and_bit()
181 	*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);  in rk3228_calc_pull_reg_and_bit()
182 	*bit *= ROCKCHIP_PULL_BITS_PER_PIN;  in rk3228_calc_pull_reg_and_bit()
190 	u8 bit, type;  in rk3228_set_pull()  local
194 		return -ENOTSUPP;  in rk3228_set_pull()
196 	rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);  in rk3228_set_pull()
197 	type = bank->pull_type[pin_num / 8];  in rk3228_set_pull()
205 	data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);  in rk3228_set_pull()
206 	data |= (ret << bit);  in rk3228_set_pull()
216 					int *reg, u8 *bit)  in rk3228_calc_drv_reg_and_bit()  argument
218 	struct rockchip_pinctrl_priv *priv = bank->priv;  in rk3228_calc_drv_reg_and_bit()
220 	*regmap = priv->regmap_base;  in rk3228_calc_drv_reg_and_bit()
222 	*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;  in rk3228_calc_drv_reg_and_bit()
225 	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);  in rk3228_calc_drv_reg_and_bit()
226 	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;  in rk3228_calc_drv_reg_and_bit()
235 	u8 bit;  in rk3228_set_drive()  local
236 	int type = bank->drv[pin_num / 8].drv_type;  in rk3228_set_drive()
238 	rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);  in rk3228_set_drive()
246 	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);  in rk3228_set_drive()
247 	data |= (ret << bit);  in rk3228_set_drive()
273 		.compatible = "rockchip,rk3228-pinctrl",