Lines Matching +full:16 +full:- +full:bit
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <dt-bindings/pinctrl/rockchip.h>
37 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
42 #define IOMUX_GPIO_ONLY BIT(0)
43 #define IOMUX_WIDTH_4BIT BIT(1)
44 #define IOMUX_SOURCE_PMU BIT(2)
45 #define IOMUX_UNROUTED BIT(3)
46 #define IOMUX_WIDTH_3BIT BIT(4)
47 #define IOMUX_8WIDTH_2BIT BIT(5)
48 #define IOMUX_WRITABLE_32BIT BIT(6)
49 #define IOMUX_L_SOURCE_PMU BIT(7)
53 * @offset: if initialized to -1 it will be autocalculated, by specifying
62 #define DRV_TYPE_IO_MASK GENMASK(31, 16)
63 #define DRV_TYPE_WRITABLE_32BIT BIT(31)
78 #define PULL_TYPE_IO_MASK GENMASK(31, 16)
79 #define PULL_TYPE_WRITABLE_32BIT BIT(31)
102 ROUTE_TYPE_INVALID = -1,
107 * @offset: if initialized to -1 it will be autocalculated, by specifying
149 { .offset = -1 }, \
150 { .offset = -1 }, \
151 { .offset = -1 }, \
152 { .offset = -1 }, \
162 { .type = iom0, .offset = -1 }, \
163 { .type = iom1, .offset = -1 }, \
164 { .type = iom2, .offset = -1 }, \
165 { .type = iom3, .offset = -1 }, \
190 { .offset = -1 }, \
191 { .offset = -1 }, \
192 { .offset = -1 }, \
193 { .offset = -1 }, \
196 { .drv_type = type0, .offset = -1 }, \
197 { .drv_type = type1, .offset = -1 }, \
198 { .drv_type = type2, .offset = -1 }, \
199 { .drv_type = type3, .offset = -1 }, \
211 { .offset = -1 }, \
212 { .offset = -1 }, \
213 { .offset = -1 }, \
214 { .offset = -1 }, \
217 { .drv_type = drv0, .offset = -1 }, \
218 { .drv_type = drv1, .offset = -1 }, \
219 { .drv_type = drv2, .offset = -1 }, \
220 { .drv_type = drv3, .offset = -1 }, \
237 { .type = iom0, .offset = -1 }, \
238 { .type = iom1, .offset = -1 }, \
239 { .type = iom2, .offset = -1 }, \
240 { .type = iom3, .offset = -1 }, \
259 { .type = iom0, .offset = -1 }, \
260 { .type = iom1, .offset = -1 }, \
261 { .type = iom2, .offset = -1 }, \
262 { .type = iom3, .offset = -1 }, \
265 { .drv_type = drv0, .offset = -1 }, \
266 { .drv_type = drv1, .offset = -1 }, \
267 { .drv_type = drv2, .offset = -1 }, \
268 { .drv_type = drv3, .offset = -1 }, \
287 { .type = iom0, .offset = -1 }, \
288 { .type = iom1, .offset = -1 }, \
289 { .type = iom2, .offset = -1 }, \
290 { .type = iom3, .offset = -1 }, \
327 * @bit: index at register.
329 * @mask: mask bit
335 u8 bit; member
380 int *reg, u8 *bit);
383 int *reg, u8 *bit);
386 int *reg, u8 *bit);
389 int *reg, u8 *bit);
404 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config()
406 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
407 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
408 return -EINVAL; in rockchip_verify_config()
414 return -EINVAL; in rockchip_verify_config()
425 .bit = 0,
431 .bit = 2,
437 .bit = 4,
443 .bit = 6,
449 .bit = 8,
455 .bit = 10,
461 .bit = 12,
467 .bit = 14,
473 .bit = 0,
479 .bit = 2,
489 .bit = 0,
496 .bit = 4,
503 .bit = 8,
510 .bit = 12,
520 .bit = 0,
526 .bit = 4,
532 .bit = 8,
538 .bit = 12,
544 .bit = 12,
554 .bit = 12,
560 .bit = 0,
566 .bit = 4,
572 .bit = 8,
578 .bit = 12,
584 .bit = 0,
590 .bit = 4,
596 .bit = 8,
602 .bit = 8,
608 .bit = 12,
618 .bit = 12,
624 .bit = 0,
630 .bit = 4,
636 .bit = 8,
642 .bit = 12,
648 .bit = 0,
654 .bit = 4,
660 .bit = 8,
666 .bit = 8,
672 .bit = 12,
678 .bit = 0,
684 .bit = 4,
688 .pin = 16,
690 .bit = 8,
696 .bit = 0,
702 .bit = 4,
712 .bit = 8,
718 .bit = 0,
724 .bit = 14,
828 int *reg, u8 *bit, int *mask) in rockchip_get_recalced_mux() argument
830 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux()
831 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux()
835 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
836 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
837 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
838 data->pin == pin) in rockchip_get_recalced_mux()
842 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
845 *reg = data->reg; in rockchip_get_recalced_mux()
846 *mask = data->mask; in rockchip_get_recalced_mux()
847 *bit = data->bit; in rockchip_get_recalced_mux()
852 /* cif-d2m0 */
857 .route_val = BIT(16 + 7),
859 /* cif-d2m1 */
864 .route_val = BIT(16 + 7) | BIT(7),
866 /* pdm-m0 */
871 .route_val = BIT(16 + 8),
873 /* pdm-m1 */
878 .route_val = BIT(16 + 8) | BIT(8),
880 /* uart2-rxm0 */
885 .route_val = BIT(16 + 10),
887 /* uart2-rxm1 */
892 .route_val = BIT(16 + 10) | BIT(10),
894 /* uart3-rxm0 */
899 .route_val = BIT(16 + 9),
901 /* uart3-rxm1 */
906 .route_val = BIT(16 + 9) | BIT(9),
917 .route_val = BIT(16 + 3),
924 .route_val = BIT(16 + 3) | BIT(3),
931 .route_val = BIT(16 + 14) | BIT(16 + 15),
938 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15),
945 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15),
951 /* spi-0 */
956 .route_val = BIT(16 + 3) | BIT(16 + 4),
958 /* spi-1 */
963 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
965 /* spi-2 */
970 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
972 /* i2s-0 */
977 .route_val = BIT(16 + 5),
979 /* i2s-1 */
984 .route_val = BIT(16 + 5) | BIT(5),
986 /* emmc-0 */
991 .route_val = BIT(16 + 6),
993 /* emmc-1 */
998 .route_val = BIT(16 + 6) | BIT(6),
1004 /* pwm0-0 */
1009 .route_val = BIT(16),
1011 /* pwm0-1 */
1016 .route_val = BIT(16) | BIT(0),
1018 /* pwm1-0 */
1023 .route_val = BIT(16 + 1),
1025 /* pwm1-1 */
1030 .route_val = BIT(16 + 1) | BIT(1),
1032 /* pwm2-0 */
1037 .route_val = BIT(16 + 2),
1039 /* pwm2-1 */
1044 .route_val = BIT(16 + 2) | BIT(2),
1046 /* pwm3-0 */
1051 .route_val = BIT(16 + 3),
1053 /* pwm3-1 */
1058 .route_val = BIT(16 + 3) | BIT(3),
1060 /* sdio-0_d0 */
1065 .route_val = BIT(16 + 4),
1067 /* sdio-1_d0 */
1072 .route_val = BIT(16 + 4) | BIT(4),
1074 /* spi-0_rx */
1079 .route_val = BIT(16 + 5),
1081 /* spi-1_rx */
1086 .route_val = BIT(16 + 5) | BIT(5),
1088 /* emmc-0_cmd */
1093 .route_val = BIT(16 + 7),
1095 /* emmc-1_cmd */
1100 .route_val = BIT(16 + 7) | BIT(7),
1102 /* uart2-0_rx */
1107 .route_val = BIT(16 + 8),
1109 /* uart2-1_rx */
1114 .route_val = BIT(16 + 8) | BIT(8),
1116 /* uart1-0_rx */
1121 .route_val = BIT(16 + 11),
1123 /* uart1-1_rx */
1128 .route_val = BIT(16 + 11) | BIT(11),
1136 .pin = 16,
1139 .route_val = BIT(16 + 12) | BIT(12),
1146 .route_val = BIT(16 + 12),
1157 .route_val = BIT(16 + 0) | BIT(0),
1164 .route_val = BIT(16 + 2) | BIT(16 + 3),
1171 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1178 .route_val = BIT(16 + 4),
1185 .route_val = BIT(16 + 4) | BIT(4),
1187 /* i2s-8ch-1-sclktxm0 */
1192 .route_val = BIT(16 + 3),
1194 /* i2s-8ch-1-sclkrxm0 */
1199 .route_val = BIT(16 + 3),
1201 /* i2s-8ch-1-sclktxm1 */
1206 .route_val = BIT(16 + 3) | BIT(3),
1208 /* i2s-8ch-1-sclkrxm1 */
1213 .route_val = BIT(16 + 3) | BIT(3),
1215 /* pdm-clkm0 */
1220 .route_val = BIT(16 + 12) | BIT(16 + 13),
1222 /* pdm-clkm1 */
1227 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1229 /* pdm-clkm2 */
1234 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1236 /* pdm-clkm-m2 */
1241 .route_val = BIT(16 + 2) | BIT(2),
1252 .route_val = BIT(16 + 0) | BIT(0),
1259 .route_val = BIT(16 + 2) | BIT(16 + 3),
1266 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1273 .route_val = BIT(16 + 8) | BIT(16 + 9),
1280 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1287 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1289 /* i2s-8ch-1-sclktxm0 */
1294 .route_val = BIT(16 + 3),
1296 /* i2s-8ch-1-sclkrxm0 */
1301 .route_val = BIT(16 + 3),
1303 /* i2s-8ch-1-sclktxm1 */
1308 .route_val = BIT(16 + 3) | BIT(3),
1310 /* i2s-8ch-1-sclkrxm1 */
1315 .route_val = BIT(16 + 3) | BIT(3),
1317 /* pdm-clkm0 */
1322 .route_val = BIT(16 + 12) | BIT(16 + 13),
1324 /* pdm-clkm1 */
1329 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1331 /* pdm-clkm2 */
1336 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1338 /* pdm-clkm-m2 */
1343 .route_val = BIT(16 + 2) | BIT(2),
1350 .route_val = BIT(16 + 9),
1357 .route_val = BIT(16 + 9) | BIT(9),
1364 .route_val = BIT(16 + 10) | BIT(16 + 11),
1371 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1378 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1385 .route_val = BIT(16 + 12) | BIT(16 + 13),
1392 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1399 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1406 .route_val = BIT(16 + 14),
1413 .route_val = BIT(16 + 14) | BIT(14),
1420 .route_val = BIT(16 + 15),
1427 .route_val = BIT(16 + 15) | BIT(15),
1438 .route_val = BIT(16) | BIT(16 + 1),
1445 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1447 /* gmac-m1_rxd0 */
1452 .route_val = BIT(16 + 2) | BIT(2),
1454 /* gmac-m1-optimized_rxd3 */
1459 .route_val = BIT(16 + 10) | BIT(10),
1466 .route_val = BIT(16 + 3),
1473 .route_val = BIT(16 + 3) | BIT(3),
1480 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1487 .route_val = BIT(16 + 6),
1494 .route_val = BIT(16 + 6) | BIT(6),
1501 .route_val = BIT(16 + 7) | BIT(7),
1505 .pin = 16,
1508 .route_val = BIT(16 + 8) | BIT(8),
1512 .pin = 16,
1515 .route_val = BIT(16 + 9) | BIT(9),
1526 .route_val = BIT(16 + 10) | BIT(16 + 11),
1530 .pin = 16,
1533 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1540 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1547 .route_val = BIT(16 + 14),
1554 .route_val = BIT(16 + 14) | BIT(14),
1562 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_mux_route()
1563 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_mux_route()
1567 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1568 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1569 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1570 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1574 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1577 *reg = data->route_offset; in rockchip_get_mux_route()
1578 *value = data->route_val; in rockchip_get_mux_route()
1580 return data->route_type; in rockchip_get_mux_route()
1585 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_mux()
1590 u8 bit; in rockchip_get_mux() local
1593 return -EINVAL; in rockchip_get_mux()
1595 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1597 return -EINVAL; in rockchip_get_mux()
1600 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1603 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1604 regmap = priv->regmap_pmu; in rockchip_get_mux()
1605 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_get_mux()
1606 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; in rockchip_get_mux()
1608 regmap = priv->regmap_base; in rockchip_get_mux()
1611 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1612 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1616 bit = (pin % 4) * 4; in rockchip_get_mux()
1621 bit = (pin % 8 % 5) * 3; in rockchip_get_mux()
1624 bit = (pin % 8) * 2; in rockchip_get_mux()
1628 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1629 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_get_mux()
1635 return ((val >> bit) & mask); in rockchip_get_mux()
1641 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_pinctrl_get_gpio_mux()
1643 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); in rockchip_pinctrl_get_gpio_mux()
1652 return -EINVAL; in rockchip_verify_mux()
1654 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1656 return -EINVAL; in rockchip_verify_mux()
1659 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1662 return -ENOTSUPP; in rockchip_verify_mux()
1672 * The register is divided into the upper and lower 16 bit. When changing
1674 * it seems the changed bits are marked in the upper 16 bit, while the
1675 * changed value gets set in the same offset in the lower 16 bit.
1676 * All pin settings seem to be 2 bit wide in both the upper and lower
1684 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_mux()
1688 u8 bit; in rockchip_set_mux() local
1695 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1698 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); in rockchip_set_mux()
1700 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1701 regmap = priv->regmap_pmu; in rockchip_set_mux()
1702 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) in rockchip_set_mux()
1703 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; in rockchip_set_mux()
1705 regmap = priv->regmap_base; in rockchip_set_mux()
1708 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1709 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1713 bit = (pin % 4) * 4; in rockchip_set_mux()
1718 bit = (pin % 8 % 5) * 3; in rockchip_set_mux()
1721 bit = (pin % 8) * 2; in rockchip_set_mux()
1725 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1726 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_set_mux()
1728 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1738 regmap_write(priv->regmap_base, route_reg, route_val); in rockchip_set_mux()
1741 regmap_write(priv->regmap_pmu, route_reg, route_val); in rockchip_set_mux()
1751 data &= ~(mask << bit); in rockchip_set_mux()
1753 data = (mask << (bit + 16)); in rockchip_set_mux()
1756 data |= (mux & mask) << bit; in rockchip_set_mux()
1766 #define PX30_PULL_BANK_STRIDE 16
1770 int *reg, u8 *bit) in px30_calc_pull_reg_and_bit() argument
1772 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_pull_reg_and_bit()
1775 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1776 *regmap = priv->regmap_pmu; in px30_calc_pull_reg_and_bit()
1779 *regmap = priv->regmap_base; in px30_calc_pull_reg_and_bit()
1783 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1784 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1788 *bit = (pin_num % PX30_PULL_PINS_PER_REG); in px30_calc_pull_reg_and_bit()
1789 *bit *= PX30_PULL_BITS_PER_PIN; in px30_calc_pull_reg_and_bit()
1796 #define PX30_DRV_BANK_STRIDE 16
1800 int *reg, u8 *bit) in px30_calc_drv_reg_and_bit() argument
1802 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_drv_reg_and_bit()
1805 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1806 *regmap = priv->regmap_pmu; in px30_calc_drv_reg_and_bit()
1809 *regmap = priv->regmap_base; in px30_calc_drv_reg_and_bit()
1813 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1814 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1818 *bit = (pin_num % PX30_DRV_PINS_PER_REG); in px30_calc_drv_reg_and_bit()
1819 *bit *= PX30_DRV_BITS_PER_PIN; in px30_calc_drv_reg_and_bit()
1824 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1825 #define PX30_SCHMITT_BANK_STRIDE 16
1831 int *reg, u8 *bit) in px30_calc_schmitt_reg_and_bit() argument
1833 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_schmitt_reg_and_bit()
1836 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1837 *regmap = priv->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1841 *regmap = priv->regmap_base; in px30_calc_schmitt_reg_and_bit()
1844 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1847 *bit = pin_num % pins_per_reg; in px30_calc_schmitt_reg_and_bit()
1856 #define RV1108_PULL_BANK_STRIDE 16
1860 int *reg, u8 *bit) in rv1108_calc_pull_reg_and_bit() argument
1862 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_pull_reg_and_bit()
1865 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1866 *regmap = priv->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1870 *regmap = priv->regmap_base; in rv1108_calc_pull_reg_and_bit()
1872 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1873 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1877 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); in rv1108_calc_pull_reg_and_bit()
1878 *bit *= RV1108_PULL_BITS_PER_PIN; in rv1108_calc_pull_reg_and_bit()
1885 #define RV1108_DRV_BANK_STRIDE 16
1889 int *reg, u8 *bit) in rv1108_calc_drv_reg_and_bit() argument
1891 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_drv_reg_and_bit()
1894 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1895 *regmap = priv->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1898 *regmap = priv->regmap_base; in rv1108_calc_drv_reg_and_bit()
1902 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1903 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1907 *bit = pin_num % RV1108_DRV_PINS_PER_REG; in rv1108_calc_drv_reg_and_bit()
1908 *bit *= RV1108_DRV_BITS_PER_PIN; in rv1108_calc_drv_reg_and_bit()
1914 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1920 int *reg, u8 *bit) in rv1108_calc_schmitt_reg_and_bit() argument
1922 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_schmitt_reg_and_bit()
1925 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1926 *regmap = priv->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1930 *regmap = priv->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1933 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1936 *bit = pin_num % pins_per_reg; in rv1108_calc_schmitt_reg_and_bit()
1945 #define RV1126_PULL_BANK_STRIDE 16
1950 int *reg, u8 *bit) in rv1126_calc_pull_reg_and_bit() argument
1952 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1126_calc_pull_reg_and_bit()
1955 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1957 *regmap = priv->regmap_base; in rv1126_calc_pull_reg_and_bit()
1959 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); in rv1126_calc_pull_reg_and_bit()
1960 *bit = pin_num % RV1126_PULL_PINS_PER_REG; in rv1126_calc_pull_reg_and_bit()
1961 *bit *= RV1126_PULL_BITS_PER_PIN; in rv1126_calc_pull_reg_and_bit()
1964 *regmap = priv->regmap_pmu; in rv1126_calc_pull_reg_and_bit()
1968 *regmap = priv->regmap_base; in rv1126_calc_pull_reg_and_bit()
1969 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; in rv1126_calc_pull_reg_and_bit()
1973 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); in rv1126_calc_pull_reg_and_bit()
1974 *bit *= RV1126_PULL_BITS_PER_PIN; in rv1126_calc_pull_reg_and_bit()
1985 int *reg, u8 *bit) in rv1126_calc_drv_reg_and_bit() argument
1987 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1126_calc_drv_reg_and_bit()
1990 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1992 *regmap = priv->regmap_base; in rv1126_calc_drv_reg_and_bit()
1994 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); in rv1126_calc_drv_reg_and_bit()
1995 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1996 *bit = pin_num % RV1126_DRV_PINS_PER_REG; in rv1126_calc_drv_reg_and_bit()
1997 *bit *= RV1126_DRV_BITS_PER_PIN; in rv1126_calc_drv_reg_and_bit()
2000 *regmap = priv->regmap_pmu; in rv1126_calc_drv_reg_and_bit()
2003 *regmap = priv->regmap_base; in rv1126_calc_drv_reg_and_bit()
2005 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; in rv1126_calc_drv_reg_and_bit()
2009 *bit = pin_num % RV1126_DRV_PINS_PER_REG; in rv1126_calc_drv_reg_and_bit()
2010 *bit *= RV1126_DRV_BITS_PER_PIN; in rv1126_calc_drv_reg_and_bit()
2015 #define RV1126_SCHMITT_BANK_STRIDE 16
2022 int *reg, u8 *bit) in rv1126_calc_schmitt_reg_and_bit() argument
2024 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1126_calc_schmitt_reg_and_bit()
2027 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
2029 *regmap = priv->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
2031 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); in rv1126_calc_schmitt_reg_and_bit()
2032 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; in rv1126_calc_schmitt_reg_and_bit()
2035 *regmap = priv->regmap_pmu; in rv1126_calc_schmitt_reg_and_bit()
2039 *regmap = priv->regmap_base; in rv1126_calc_schmitt_reg_and_bit()
2042 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; in rv1126_calc_schmitt_reg_and_bit()
2045 *bit = pin_num % pins_per_reg; in rv1126_calc_schmitt_reg_and_bit()
2054 #define RK1808_PULL_BANK_STRIDE 16
2059 int *reg, u8 *bit) in rk1808_calc_pull_reg_and_bit() argument
2061 struct rockchip_pinctrl_priv *priv = bank->priv; in rk1808_calc_pull_reg_and_bit()
2063 if (bank->bank_num == 0) { in rk1808_calc_pull_reg_and_bit()
2064 *regmap = priv->regmap_pmu; in rk1808_calc_pull_reg_and_bit()
2068 *regmap = priv->regmap_base; in rk1808_calc_pull_reg_and_bit()
2072 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); in rk1808_calc_pull_reg_and_bit()
2073 *bit *= RK1808_PULL_BITS_PER_PIN; in rk1808_calc_pull_reg_and_bit()
2080 #define RK1808_DRV_BANK_STRIDE 16
2085 int *reg, u8 *bit) in rk1808_calc_drv_reg_and_bit() argument
2087 struct rockchip_pinctrl_priv *priv = bank->priv; in rk1808_calc_drv_reg_and_bit()
2089 if (bank->bank_num == 0) { in rk1808_calc_drv_reg_and_bit()
2090 *regmap = priv->regmap_pmu; in rk1808_calc_drv_reg_and_bit()
2093 *regmap = priv->regmap_base; in rk1808_calc_drv_reg_and_bit()
2098 *bit = pin_num % RK1808_DRV_PINS_PER_REG; in rk1808_calc_drv_reg_and_bit()
2099 *bit *= RK1808_DRV_BITS_PER_PIN; in rk1808_calc_drv_reg_and_bit()
2104 #define RK1808_SCHMITT_BANK_STRIDE 16
2110 int *reg, u8 *bit) in rk1808_calc_schmitt_reg_and_bit() argument
2112 struct rockchip_pinctrl_priv *priv = bank->priv; in rk1808_calc_schmitt_reg_and_bit()
2114 if (bank->bank_num == 0) { in rk1808_calc_schmitt_reg_and_bit()
2115 *regmap = priv->regmap_pmu; in rk1808_calc_schmitt_reg_and_bit()
2118 *regmap = priv->regmap_base; in rk1808_calc_schmitt_reg_and_bit()
2120 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; in rk1808_calc_schmitt_reg_and_bit()
2123 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; in rk1808_calc_schmitt_reg_and_bit()
2129 #define RK2928_PULL_PINS_PER_REG 16
2134 int *reg, u8 *bit) in rk2928_calc_pull_reg_and_bit() argument
2136 struct rockchip_pinctrl_priv *priv = bank->priv; in rk2928_calc_pull_reg_and_bit()
2138 *regmap = priv->regmap_base; in rk2928_calc_pull_reg_and_bit()
2140 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
2143 *bit = pin_num % RK2928_PULL_PINS_PER_REG; in rk2928_calc_pull_reg_and_bit()
2150 int *reg, u8 *bit) in rk3128_calc_pull_reg_and_bit() argument
2152 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3128_calc_pull_reg_and_bit()
2154 *regmap = priv->regmap_base; in rk3128_calc_pull_reg_and_bit()
2156 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
2159 *bit = pin_num % RK2928_PULL_PINS_PER_REG; in rk3128_calc_pull_reg_and_bit()
2165 #define RK3188_PULL_BANK_STRIDE 16
2170 int *reg, u8 *bit) in rk3188_calc_pull_reg_and_bit() argument
2172 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3188_calc_pull_reg_and_bit()
2175 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
2176 *regmap = priv->regmap_pmu; in rk3188_calc_pull_reg_and_bit()
2180 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3188_calc_pull_reg_and_bit()
2181 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
2183 *regmap = priv->regmap_base; in rk3188_calc_pull_reg_and_bit()
2187 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
2188 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
2196 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
2197 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3188_calc_pull_reg_and_bit()
2204 int *reg, u8 *bit) in rk3288_calc_pull_reg_and_bit() argument
2206 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_calc_pull_reg_and_bit()
2209 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
2210 *regmap = priv->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
2214 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3288_calc_pull_reg_and_bit()
2215 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
2217 *regmap = priv->regmap_base; in rk3288_calc_pull_reg_and_bit()
2221 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
2222 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
2225 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3288_calc_pull_reg_and_bit()
2226 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
2234 #define RK3288_DRV_BANK_STRIDE 16
2238 int *reg, u8 *bit) in rk3288_calc_drv_reg_and_bit() argument
2240 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_calc_drv_reg_and_bit()
2243 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
2244 *regmap = priv->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
2248 *bit = pin_num % RK3288_DRV_PINS_PER_REG; in rk3288_calc_drv_reg_and_bit()
2249 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
2251 *regmap = priv->regmap_base; in rk3288_calc_drv_reg_and_bit()
2255 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
2256 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
2259 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3288_calc_drv_reg_and_bit()
2260 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
2268 int *reg, u8 *bit) in rk3228_calc_pull_reg_and_bit() argument
2270 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3228_calc_pull_reg_and_bit()
2272 *regmap = priv->regmap_base; in rk3228_calc_pull_reg_and_bit()
2274 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
2277 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3228_calc_pull_reg_and_bit()
2278 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3228_calc_pull_reg_and_bit()
2285 int *reg, u8 *bit) in rk3228_calc_drv_reg_and_bit() argument
2287 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3228_calc_drv_reg_and_bit()
2289 *regmap = priv->regmap_base; in rk3228_calc_drv_reg_and_bit()
2291 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
2294 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3228_calc_drv_reg_and_bit()
2295 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3228_calc_drv_reg_and_bit()
2302 int *reg, u8 *bit) in rk3308_calc_pull_reg_and_bit() argument
2304 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3308_calc_pull_reg_and_bit()
2306 *regmap = priv->regmap_base; in rk3308_calc_pull_reg_and_bit()
2308 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
2311 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3308_calc_pull_reg_and_bit()
2312 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3308_calc_pull_reg_and_bit()
2319 int *reg, u8 *bit) in rk3308_calc_drv_reg_and_bit() argument
2321 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3308_calc_drv_reg_and_bit()
2323 *regmap = priv->regmap_base; in rk3308_calc_drv_reg_and_bit()
2325 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
2328 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3308_calc_drv_reg_and_bit()
2329 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3308_calc_drv_reg_and_bit()
2333 #define RK3308_SCHMITT_BANK_STRIDE 16
2339 int *reg, u8 *bit) in rk3308_calc_schmitt_reg_and_bit() argument
2341 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3308_calc_schmitt_reg_and_bit()
2343 *regmap = priv->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
2346 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
2348 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; in rk3308_calc_schmitt_reg_and_bit()
2358 int *reg, u8 *bit) in rk3368_calc_pull_reg_and_bit() argument
2360 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_pull_reg_and_bit()
2363 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
2364 *regmap = priv->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
2368 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3368_calc_pull_reg_and_bit()
2369 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
2371 *regmap = priv->regmap_base; in rk3368_calc_pull_reg_and_bit()
2375 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
2376 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
2379 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3368_calc_pull_reg_and_bit()
2380 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
2389 int *reg, u8 *bit) in rk3368_calc_drv_reg_and_bit() argument
2391 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_drv_reg_and_bit()
2394 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
2395 *regmap = priv->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
2399 *bit = pin_num % RK3288_DRV_PINS_PER_REG; in rk3368_calc_drv_reg_and_bit()
2400 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
2402 *regmap = priv->regmap_base; in rk3368_calc_drv_reg_and_bit()
2406 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
2407 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2410 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); in rk3368_calc_drv_reg_and_bit()
2411 *bit *= RK3288_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
2421 int *reg, u8 *bit) in rk3399_calc_pull_reg_and_bit() argument
2423 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_pull_reg_and_bit()
2425 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_pull_reg_and_bit()
2426 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2427 *regmap = priv->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
2430 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2433 *bit = pin_num % RK3188_PULL_PINS_PER_REG; in rk3399_calc_pull_reg_and_bit()
2434 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3399_calc_pull_reg_and_bit()
2436 *regmap = priv->regmap_base; in rk3399_calc_pull_reg_and_bit()
2440 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
2441 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2444 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); in rk3399_calc_pull_reg_and_bit()
2445 *bit *= RK3188_PULL_BITS_PER_PIN; in rk3399_calc_pull_reg_and_bit()
2451 int *reg, u8 *bit) in rk3399_calc_drv_reg_and_bit() argument
2453 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_drv_reg_and_bit()
2456 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_drv_reg_and_bit()
2457 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2458 *regmap = priv->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
2460 *regmap = priv->regmap_base; in rk3399_calc_drv_reg_and_bit()
2462 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2463 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2464 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2465 *bit = (pin_num % 8) * 3; in rk3399_calc_drv_reg_and_bit()
2467 *bit = (pin_num % 8) * 2; in rk3399_calc_drv_reg_and_bit()
2471 #define RK3308_SLEW_RATE_BANK_STRIDE 16
2477 int *reg, u8 *bit) in rk3308_calc_slew_rate_reg_and_bit() argument
2479 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3308_calc_slew_rate_reg_and_bit()
2482 *regmap = priv->regmap_base; in rk3308_calc_slew_rate_reg_and_bit()
2484 *reg += (bank->bank_num) * RK3308_SLEW_RATE_BANK_STRIDE; in rk3308_calc_slew_rate_reg_and_bit()
2488 *bit = pin_num % pins_per_reg; in rk3308_calc_slew_rate_reg_and_bit()
2492 { 2, 4, 8, 12, -1, -1, -1, -1 },
2493 { 3, 6, 9, 12, -1, -1, -1, -1 },
2494 { 5, 10, 15, 20, -1, -1, -1, -1 },
2495 { 4, 6, 8, 10, 12, 14, 16, 18 },
2496 { 4, 7, 10, 13, 16, 19, 22, 26 },
2503 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_drive_perpin()
2504 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_drive_perpin()
2508 u8 bit; in rockchip_set_drive_perpin() local
2510 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); in rockchip_set_drive_perpin()
2512 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, in rockchip_set_drive_perpin()
2515 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2516 if (ctrl->type == RV1126) { in rockchip_set_drive_perpin()
2524 ret = -EINVAL; in rockchip_set_drive_perpin()
2542 if (ctrl->type == RK3308) { /* RK3308B-S */ in rockchip_set_drive_perpin()
2545 data = 0x3 << (bit + 16); in rockchip_set_drive_perpin()
2546 data |= ((regval & 0x3) << bit); in rockchip_set_drive_perpin()
2552 rk3308_calc_slew_rate_reg_and_bit(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2553 data = BIT(bit + 16) | (((regval > 3) ? 1 : 0) << bit); in rockchip_set_drive_perpin()
2558 dev_err(info->dev, "unsupported type DRV_TYPE_IO_SMIC\n"); in rockchip_set_drive_perpin()
2559 return -EINVAL; in rockchip_set_drive_perpin()
2563 switch (bit) { in rockchip_set_drive_perpin()
2569 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2570 * over 2 registers, the bit data[15] contains bit 0 in rockchip_set_drive_perpin()
2576 data |= BIT(31); in rockchip_set_drive_perpin()
2581 temp |= (0x3 << 16); in rockchip_set_drive_perpin()
2589 bit -= 16; in rockchip_set_drive_perpin()
2592 debug("unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2593 bit, drv_type); in rockchip_set_drive_perpin()
2594 return -EINVAL; in rockchip_set_drive_perpin()
2605 return -EINVAL; in rockchip_set_drive_perpin()
2609 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { in rockchip_set_drive_perpin()
2611 data &= ~(((1 << rmask_bits) - 1) << bit); in rockchip_set_drive_perpin()
2614 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2617 data |= (ret << bit); in rockchip_set_drive_perpin()
2640 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_pull()
2641 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_pull()
2644 u8 bit; in rockchip_set_pull() local
2647 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, in rockchip_set_pull()
2651 if (ctrl->type == RK3066B) in rockchip_set_pull()
2652 return pull ? -EINVAL : 0; in rockchip_set_pull()
2654 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2656 switch (ctrl->type) { in rockchip_set_pull()
2659 data = BIT(bit + 16); in rockchip_set_pull()
2661 data |= BIT(bit); in rockchip_set_pull()
2677 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); in rockchip_set_pull()
2678 ret = -EINVAL; in rockchip_set_pull()
2692 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { in rockchip_set_pull()
2694 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); in rockchip_set_pull()
2697 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2700 data |= (ret << bit); in rockchip_set_pull()
2705 return -EINVAL; in rockchip_set_pull()
2712 #define RK3328_SCHMITT_PINS_PER_REG 16
2719 int *reg, u8 *bit) in rk3328_calc_schmitt_reg_and_bit() argument
2721 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3328_calc_schmitt_reg_and_bit()
2723 *regmap = priv->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2726 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2728 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; in rk3328_calc_schmitt_reg_and_bit()
2736 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_schmitt()
2737 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_schmitt()
2740 u8 bit; in rockchip_set_schmitt() local
2743 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, in rockchip_set_schmitt()
2746 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2751 data = BIT(bit + 16) | (enable << bit); in rockchip_set_schmitt()
2758 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16
2759 #define PX30_SLEW_RATE_BANK_STRIDE 16
2765 int *reg, u8 *bit) in px30_calc_slew_rate_reg_and_bit() argument
2767 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_slew_rate_reg_and_bit()
2770 if (bank->bank_num == 0) { in px30_calc_slew_rate_reg_and_bit()
2771 *regmap = priv->regmap_pmu; in px30_calc_slew_rate_reg_and_bit()
2775 *regmap = priv->regmap_base; in px30_calc_slew_rate_reg_and_bit()
2778 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_slew_rate_reg_and_bit()
2781 *bit = pin_num % pins_per_reg; in px30_calc_slew_rate_reg_and_bit()
2789 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_set_slew_rate()
2790 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_slew_rate()
2793 u8 bit; in rockchip_set_slew_rate() local
2796 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, in rockchip_set_slew_rate()
2799 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_slew_rate()
2804 data = BIT(bit + 16) | (speed << bit); in rockchip_set_slew_rate()
2815 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2841 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_pinconf_set()
2842 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_pinconf_set()
2857 return -ENOTSUPP; in rockchip_pinconf_set()
2860 return -EINVAL; in rockchip_pinconf_set()
2868 if (!ctrl->drv_calc_reg) in rockchip_pinconf_set()
2869 return -ENOTSUPP; in rockchip_pinconf_set()
2877 if (!ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2878 return -ENOTSUPP; in rockchip_pinconf_set()
2886 if (!ctrl->slew_rate_calc_reg) in rockchip_pinconf_set()
2887 return -ENOTSUPP; in rockchip_pinconf_set()
2890 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2903 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
2904 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
2905 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
2906 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
2907 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
2908 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
2909 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
2910 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
2911 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
2912 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
2925 if (!strcmp(property, p->property)) { in rockchip_pinconf_prop_name_to_param()
2926 *default_value = p->default_value; in rockchip_pinconf_prop_name_to_param()
2927 return p->param; in rockchip_pinconf_prop_name_to_param()
2932 return -EPERM; in rockchip_pinconf_prop_name_to_param()
2939 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
2953 const void *blob = gd->fdt_blob;
2958 return -EINVAL;
2965 return -EINVAL;
2981 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
2987 return -ENODEV;
2990 for (pp = np->properties; pp; pp = pp->next) {
2991 prop_name = pp->name;
2992 prop_len = pp->length;
2993 value = pp->value;
3000 return -ENOENT;
3012 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
3028 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
3030 return ctrl->nr_pins;
3055 grf_offs = ctrl->grf_mux_offset;
3056 pmu_offs = ctrl->pmu_mux_offset;
3057 drv_pmu_offs = ctrl->pmu_drv_offset;
3058 drv_grf_offs = ctrl->grf_drv_offset;
3059 bank = ctrl->pin_banks;
3061 /* Ctrl data re-initialize for some Socs */
3062 if (ctrl->ctrl_data_re_init) {
3063 if (ctrl->ctrl_data_re_init(ctrl))
3068 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3071 bank->priv = priv;
3072 bank->pin_base = nr_pins;
3073 nr_pins += bank->nr_pins;
3077 struct rockchip_iomux *iom = &bank->iomux[j];
3078 struct rockchip_drv *drv = &bank->drv[j];
3081 if (bank_pins >= bank->nr_pins)
3085 if (iom->offset >= 0) {
3086 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3087 pmu_offs = iom->offset;
3089 grf_offs = iom->offset;
3091 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3092 (iom->type & IOMUX_L_SOURCE_PMU)) ?
3097 if (drv->offset >= 0) {
3098 if (iom->type & IOMUX_SOURCE_PMU)
3099 drv_pmu_offs = drv->offset;
3101 drv_grf_offs = drv->offset;
3103 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3108 i, j, iom->offset, drv->offset);
3112 * 4bit iomux'es are spread over two registers.
3114 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3117 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3124 * 3bit drive-strenth'es are spread over two registers.
3126 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3127 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3132 if (iom->type & IOMUX_SOURCE_PMU)
3140 /* calculate the per-bank recalced_mask */
3141 for (j = 0; j < ctrl->niomux_recalced; j++) {
3144 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3145 pin = ctrl->iomux_recalced[j].pin;
3146 bank->recalced_mask |= BIT(pin);
3150 /* calculate the per-bank route_mask */
3151 for (j = 0; j < ctrl->niomux_routes; j++) {
3154 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3155 pin = ctrl->iomux_routes[j].pin;
3156 bank->route_mask |= BIT(pin);
3161 WARN_ON(nr_pins != ctrl->nr_pins);
3173 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10))
3174 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
3175 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
3178 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11))
3179 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7))
3180 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3))
3189 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13,
3196 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15,
3222 /* get grf-reg base address */
3226 return -ENODEV;
3228 priv->regmap_base = regmap;
3230 /* option: get pmu-reg base address */
3234 /* get pmugrf-reg base address */
3238 return -ENODEV;
3240 priv->regmap_pmu = regmap;
3246 return -EINVAL;
3250 if (ctrl->soc_data_init) {
3251 ret = ctrl->soc_data_init(priv);
3256 priv->ctrl = (struct rockchip_pin_ctrl *)ctrl;
3287 .label = "PX30-GPIO",
3313 .label = "RV1108-GPIO",
3354 .label = "RV1126-GPIO",
3399 .label = "RK1808-GPIO",
3421 .label = "RK2928-GPIO",
3437 .label = "RK3036-GPIO",
3449 PIN_BANK(6, 16, "gpio6"),
3456 .label = "RK3066a-GPIO",
3473 .label = "RK3066b-GPIO",
3489 .label = "RK3128-GPIO",
3510 .label = "RK3188-GPIO",
3527 .label = "RK3228-GPIO",
3574 PIN_BANK(8, 16, "gpio8"),
3581 .label = "RK3288-GPIO",
3618 .label = "RK3308-GPIO",
3634 .label = "RK3308-GPIO",
3665 .label = "RK3328-GPIO",
3692 .label = "RK3368-GPIO",
3712 -1,
3713 -1,
3757 .label = "RK3399-GPIO",
3770 { .compatible = "rockchip,px30-pinctrl",
3772 { .compatible = "rockchip,rv1108-pinctrl",
3774 { .compatible = "rockchip,rv1126-pinctrl-legency",
3776 { .compatible = "rockchip,rk1808-pinctrl",
3778 { .compatible = "rockchip,rk2928-pinctrl",
3780 { .compatible = "rockchip,rk3036-pinctrl",
3782 { .compatible = "rockchip,rk3066a-pinctrl",
3784 { .compatible = "rockchip,rk3066b-pinctrl",
3786 { .compatible = "rockchip,rk3128-pinctrl",
3788 { .compatible = "rockchip,rk3188-pinctrl",
3790 { .compatible = "rockchip,rk3228-pinctrl",
3792 { .compatible = "rockchip,rk3288-pinctrl",
3794 { .compatible = "rockchip,rk3308-pinctrl",
3796 { .compatible = "rockchip,rk3328-pinctrl",
3798 { .compatible = "rockchip,rk3368-pinctrl",
3800 { .compatible = "rockchip,rk3399-pinctrl",