1170 	val = readl(&eqos->dma_regs->mode);  in eqos_init()
1172 	writel(val, &eqos->dma_regs->mode);  in eqos_init()
1174 		if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))  in eqos_init()
1411 	setbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1415 	clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1421 	setbits_le32(&eqos->dma_regs->ch0_control,  in eqos_enable()
1433 	clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1438 	clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1447 	writel(val, &eqos->dma_regs->sysbus_mode);  in eqos_enable()
1464 	writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);  in eqos_enable()
1465 	writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);  in eqos_enable()
1467 	       &eqos->dma_regs->ch0_txdesc_ring_length);  in eqos_enable()
1469 	writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);  in eqos_enable()
1470 	writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);  in eqos_enable()
1472 	       &eqos->dma_regs->ch0_rxdesc_ring_length);  in eqos_enable()
1475 	setbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1477 	setbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1490 	writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);  in eqos_enable()
1521 	clrbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_stop()
1550 	clrbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_stop()
1590 		&eqos->dma_regs->ch0_txdesc_tail_pointer);  in eqos_send()
1664 	writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);  in eqos_free_pkt()
2031 	eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);  in eqos_probe()