272 			     pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
314 		rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
337 	mask = pll->mode_mask << shift;  in rk3036_pll_get_rate()
424 		     pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
428 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
432 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
436 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
467 	rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
471 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
481 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
491 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
531 		mode = (con & (pll->mode_mask << shift)) >> shift;  in rk3588_pll_get_rate()
575 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
579 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_get_rate()
583 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
604 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()
608 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_set_rate()
612 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()