229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)  in rockchip_get_pll_settings()  argument
233 	while (rate_table->rate) {  in rockchip_get_pll_settings()
234 		if (rate_table->rate == rate)  in rockchip_get_pll_settings()
238 	if (rate_table->rate != rate) {  in rockchip_get_pll_settings()
240 			return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);  in rockchip_get_pll_settings()
242 			return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);  in rockchip_get_pll_settings()
252 	const struct rockchip_pll_rate_table *rate;  in rk3036_pll_set_rate()  local
255 	rate = rockchip_get_pll_settings(pll, drate);  in rk3036_pll_set_rate()
256 	if (!rate) {  in rk3036_pll_set_rate()
262 	      __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);  in rk3036_pll_set_rate()
264 	      __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);  in rk3036_pll_set_rate()
283 		     (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |  in rk3036_pll_set_rate()
284 		     rate->fbdiv);  in rk3036_pll_set_rate()
288 		     (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |  in rk3036_pll_set_rate()
289 		     rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));  in rk3036_pll_set_rate()
290 	if (!rate->dsmpd) {  in rk3036_pll_set_rate()
293 			     rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);  in rk3036_pll_set_rate()
296 			    (rate->frac << RK3036_PLLCON2_FRAC_SHIFT),  in rk3036_pll_set_rate()
332 	ulong rate;  in rk3036_pll_get_rate()  local
364 		rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;  in rk3036_pll_get_rate()
372 			rate += frac_rate;  in rk3036_pll_get_rate()
374 		return rate;  in rk3036_pll_get_rate()
405 	const struct rockchip_pll_rate_table *rate;  in rk3588_pll_set_rate()  local
407 	rate = rockchip_get_pll_settings(pll, drate);  in rk3588_pll_set_rate()
408 	if (!rate) {  in rk3588_pll_set_rate()
414 	      __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);  in rk3588_pll_set_rate()
445 		     (rate->m << RK3588_PLLCON0_M_SHIFT));  in rk3588_pll_set_rate()
449 		     (rate->p << RK3588_PLLCON1_P_SHIFT |  in rk3588_pll_set_rate()
450 		     rate->s << RK3588_PLLCON1_S_SHIFT));  in rk3588_pll_set_rate()
451 	if (rate->k) {  in rk3588_pll_set_rate()
454 			     rate->k << RK3588_PLLCON2_K_SHIFT);  in rk3588_pll_set_rate()
524 	u64 rate, postdiv;  in rk3588_pll_get_rate()  local
549 		rate = OSC_HZ / p;  in rk3588_pll_get_rate()
550 		rate *= m;  in rk3588_pll_get_rate()
557 			rate += frac_rate64;  in rk3588_pll_get_rate()
559 		rate = rate >> s;  in rk3588_pll_get_rate()
560 		return rate;  in rk3588_pll_get_rate()
571 	ulong rate = 0;  in rockchip_pll_get_rate()  local
576 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
580 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
584 		rate = rk3588_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
590 	return rate;  in rockchip_pll_get_rate()
624 			  ulong rate)  in rockchip_get_cpu_settings()  argument
628 	while (ps->rate) {  in rockchip_get_cpu_settings()
629 		if (ps->rate == rate)  in rockchip_get_cpu_settings()
633 	if (ps->rate != rate)  in rockchip_get_cpu_settings()