Lines Matching +full:pll +full:- +full:1
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
61 m -= n; in gcd()
67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
68 * Formulas also embedded within the Fractional PLL Verilog model:
69 * If DSMPD = 1 (DSM is disabled, "integer mode")
73 * FOUTVCO = Fractional PLL non-divided output frequency
74 * FOUTPOSTDIV = Fractional PLL divided output frequency
76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
77 * REFDIV = Fractional PLL input reference clock divider
90 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) { in rockchip_pll_clk_set_postdiv()
91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { in rockchip_pll_clk_set_postdiv()
103 *postdiv1 = 1; in rockchip_pll_clk_set_postdiv()
104 *postdiv2 = 1; in rockchip_pll_clk_set_postdiv()
114 /* FIXME set postdiv1/2 always 1*/ in rockchip_pll_clk_set_by_auto()
124 rate_table->postdiv1 = postdiv1; in rockchip_pll_clk_set_by_auto()
125 rate_table->postdiv2 = postdiv2; in rockchip_pll_clk_set_by_auto()
126 rate_table->dsmpd = 1; in rockchip_pll_clk_set_by_auto()
132 rate_table->refdiv = fin_hz / clk_gcd; in rockchip_pll_clk_set_by_auto()
133 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
135 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
140 rate_table->refdiv, in rockchip_pll_clk_set_by_auto()
141 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
142 rate_table->postdiv2); in rockchip_pll_clk_set_by_auto()
147 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
149 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
150 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
152 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
154 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
158 fin_64 = fin_64 / rate_table->refdiv; in rockchip_pll_clk_set_by_auto()
161 rate_table->frac = frac_64; in rockchip_pll_clk_set_by_auto()
162 if (rate_table->frac > 0) in rockchip_pll_clk_set_by_auto()
163 rate_table->dsmpd = 0; in rockchip_pll_clk_set_by_auto()
164 debug("frac = %x\n", rate_table->frac); in rockchip_pll_clk_set_by_auto()
192 rate_table->p = p; in rk3588_pll_clk_set_by_auto()
193 rate_table->m = m; in rk3588_pll_clk_set_by_auto()
194 rate_table->s = s; in rk3588_pll_clk_set_by_auto()
195 rate_table->k = 0; in rk3588_pll_clk_set_by_auto()
208 for (p = 1; p <= 4; p++) { in rk3588_pll_clk_set_by_auto()
210 if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) { in rk3588_pll_clk_set_by_auto()
211 rate_table->p = p; in rk3588_pll_clk_set_by_auto()
212 rate_table->m = m; in rk3588_pll_clk_set_by_auto()
213 rate_table->s = s; in rk3588_pll_clk_set_by_auto()
215 ffrac = fvco - (m * fref); in rk3588_pll_clk_set_by_auto()
217 rate_table->k = fout / fref; in rk3588_pll_clk_set_by_auto()
229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
231 struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
233 while (rate_table->rate) { in rockchip_get_pll_settings()
234 if (rate_table->rate == rate) in rockchip_get_pll_settings()
238 if (rate_table->rate != rate) { in rockchip_get_pll_settings()
239 if (pll->type == pll_rk3588) in rockchip_get_pll_settings()
248 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate() argument
255 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
258 return -EINVAL; in rk3036_pll_set_rate()
262 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
264 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
267 * When power on or changing PLL setting, in rk3036_pll_set_rate()
268 * we must force PLL into slow mode to ensure output stable clock. in rk3036_pll_set_rate()
270 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { in rk3036_pll_set_rate()
271 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
272 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
273 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3036_pll_set_rate()
277 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
278 1 << RK3036_PLLCON1_PWRDOWN_SHIT); in rk3036_pll_set_rate()
280 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
283 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) | in rk3036_pll_set_rate()
284 rate->fbdiv); in rk3036_pll_set_rate()
285 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
288 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | in rk3036_pll_set_rate()
289 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); in rk3036_pll_set_rate()
290 if (!rate->dsmpd) { in rk3036_pll_set_rate()
291 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
293 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT); in rk3036_pll_set_rate()
294 writel((readl(base + pll->con_offset + 0x8) & in rk3036_pll_set_rate()
296 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), in rk3036_pll_set_rate()
297 base + pll->con_offset + 0x8); in rk3036_pll_set_rate()
301 rk_clrreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
302 1 << RK3036_PLLCON1_PWRDOWN_SHIT); in rk3036_pll_set_rate()
304 /* waiting for pll lock */ in rk3036_pll_set_rate()
305 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { in rk3036_pll_set_rate()
306 udelay(1); in rk3036_pll_set_rate()
307 timeout--; in rk3036_pll_set_rate()
310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
311 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id); in rk3036_pll_set_rate()
313 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { in rk3036_pll_set_rate()
314 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
315 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); in rk3036_pll_set_rate()
318 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", in rk3036_pll_set_rate()
319 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
320 readl(base + pll->con_offset + 0x4), in rk3036_pll_set_rate()
321 readl(base + pll->con_offset + 0x8), in rk3036_pll_set_rate()
322 readl(base + pll->mode_offset)); in rk3036_pll_set_rate()
327 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, in rk3036_pll_get_rate() argument
335 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
336 shift = pll->mode_shift; in rk3036_pll_get_rate()
337 mask = pll->mode_mask << shift; in rk3036_pll_get_rate()
339 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) in rk3036_pll_get_rate()
349 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
354 con = readl(base + pll->con_offset + 0x4); in rk3036_pll_get_rate()
361 con = readl(base + pll->con_offset + 0x8); in rk3036_pll_get_rate()
401 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, in rk3588_pll_set_rate() argument
407 rate = rockchip_get_pll_settings(pll, drate); in rk3588_pll_set_rate()
410 return -EINVAL; in rk3588_pll_set_rate()
414 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rk3588_pll_set_rate()
417 * When power on or changing PLL setting, in rk3588_pll_set_rate()
418 * we must force PLL into slow mode to ensure output stable clock. in rk3588_pll_set_rate()
421 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1); in rk3588_pll_set_rate()
423 rk_clrsetreg(base + pll->mode_offset, in rk3588_pll_set_rate()
424 pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
425 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3588_pll_set_rate()
428 pll->mode_mask << 6, in rk3588_pll_set_rate()
430 else if (pll_id == 1) in rk3588_pll_set_rate()
432 pll->mode_mask << 6, in rk3588_pll_set_rate()
436 pll->mode_mask << 14, in rk3588_pll_set_rate()
440 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
443 rk_clrsetreg(base + pll->con_offset, in rk3588_pll_set_rate()
445 (rate->m << RK3588_PLLCON0_M_SHIFT)); in rk3588_pll_set_rate()
446 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
449 (rate->p << RK3588_PLLCON1_P_SHIFT | in rk3588_pll_set_rate()
450 rate->s << RK3588_PLLCON1_S_SHIFT)); in rk3588_pll_set_rate()
451 if (rate->k) { in rk3588_pll_set_rate()
452 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), in rk3588_pll_set_rate()
454 rate->k << RK3588_PLLCON2_K_SHIFT); in rk3588_pll_set_rate()
457 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
460 /* waiting for pll lock */ in rk3588_pll_set_rate()
461 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & in rk3588_pll_set_rate()
463 udelay(1); in rk3588_pll_set_rate()
464 debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id); in rk3588_pll_set_rate()
467 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
468 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); in rk3588_pll_set_rate()
471 pll->mode_mask << 6, in rk3588_pll_set_rate()
476 rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1), in rk3588_pll_set_rate()
479 } else if (pll_id == 1) { in rk3588_pll_set_rate()
481 pll->mode_mask << 6, in rk3588_pll_set_rate()
486 rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1), in rk3588_pll_set_rate()
491 pll->mode_mask << 14, in rk3588_pll_set_rate()
508 rk_clrsetreg(base + 0x84c, 0x1 << 1, 0); in rk3588_pll_set_rate()
510 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n", in rk3588_pll_set_rate()
511 pll, readl(base + pll->con_offset), in rk3588_pll_set_rate()
512 readl(base + pll->con_offset + 0x4), in rk3588_pll_set_rate()
513 readl(base + pll->con_offset + 0x8), in rk3588_pll_set_rate()
514 readl(base + pll->mode_offset)); in rk3588_pll_set_rate()
519 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, in rk3588_pll_get_rate() argument
526 con = readl(base + pll->mode_offset); in rk3588_pll_get_rate()
527 shift = pll->mode_shift; in rk3588_pll_get_rate()
531 mode = (con & (pll->mode_mask << shift)) >> shift; in rk3588_pll_get_rate()
537 con = readl(base + pll->con_offset); in rk3588_pll_get_rate()
540 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); in rk3588_pll_get_rate()
545 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); in rk3588_pll_get_rate()
567 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate() argument
573 switch (pll->type) { in rockchip_pll_get_rate()
575 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
576 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
579 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_get_rate()
580 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
583 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
584 rate = rk3588_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
587 printf("%s: Unknown pll type for pll clk %ld\n", in rockchip_pll_get_rate()
593 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, in rockchip_pll_set_rate() argument
599 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
602 switch (pll->type) { in rockchip_pll_set_rate()
604 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
605 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
608 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_set_rate()
609 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
612 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
613 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
616 printf("%s: Unknown pll type for pll clk %ld\n", in rockchip_pll_set_rate()
628 while (ps->rate) { in rockchip_get_cpu_settings()
629 if (ps->rate == rate) in rockchip_get_cpu_settings()
633 if (ps->rate != rate) in rockchip_get_cpu_settings()