67  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
68  * Formulas also embedded within the Fractional PLL Verilog model:
73  * FOUTVCO = Fractional PLL non-divided output frequency
74  * FOUTPOSTDIV = Fractional PLL divided output frequency
76  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
77  * REFDIV = Fractional PLL input reference clock divider
229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)  in rockchip_get_pll_settings()  argument
231 	struct rockchip_pll_rate_table  *rate_table = pll->rate_table;  in rockchip_get_pll_settings()
239 		if (pll->type == pll_rk3588)  in rockchip_get_pll_settings()
248 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,  in rk3036_pll_set_rate()  argument
255 	rate = rockchip_get_pll_settings(pll, drate);  in rk3036_pll_set_rate()
267 	 * When power on or changing PLL setting,  in rk3036_pll_set_rate()
268 	 * we must force PLL into slow mode to ensure output stable clock.  in rk3036_pll_set_rate()
270 	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {  in rk3036_pll_set_rate()
271 		rk_clrsetreg(base + pll->mode_offset,  in rk3036_pll_set_rate()
272 			     pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
273 			     RKCLK_PLL_MODE_SLOW << pll->mode_shift);  in rk3036_pll_set_rate()
277 	rk_setreg(base + pll->con_offset + 0x4,  in rk3036_pll_set_rate()
280 	rk_clrsetreg(base + pll->con_offset,  in rk3036_pll_set_rate()
285 	rk_clrsetreg(base + pll->con_offset + 0x4,  in rk3036_pll_set_rate()
291 		rk_clrsetreg(base + pll->con_offset + 0x4,  in rk3036_pll_set_rate()
294 		writel((readl(base + pll->con_offset + 0x8) &  in rk3036_pll_set_rate()
297 			    base + pll->con_offset + 0x8);  in rk3036_pll_set_rate()
301 	rk_clrreg(base + pll->con_offset + 0x4,  in rk3036_pll_set_rate()
304 	/* waiting for pll lock */  in rk3036_pll_set_rate()
305 	while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) {  in rk3036_pll_set_rate()
310 	if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))  in rk3036_pll_set_rate()
311 		printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id);  in rk3036_pll_set_rate()
313 	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {  in rk3036_pll_set_rate()
314 		rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
315 			     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);  in rk3036_pll_set_rate()
318 	debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",  in rk3036_pll_set_rate()
319 	      pll, readl(base + pll->con_offset),  in rk3036_pll_set_rate()
320 	      readl(base + pll->con_offset + 0x4),  in rk3036_pll_set_rate()
321 	      readl(base + pll->con_offset + 0x8),  in rk3036_pll_set_rate()
322 	      readl(base + pll->mode_offset));  in rk3036_pll_set_rate()
327 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,  in rk3036_pll_get_rate()  argument
335 	con = readl(base + pll->mode_offset);  in rk3036_pll_get_rate()
336 	shift = pll->mode_shift;  in rk3036_pll_get_rate()
337 	mask = pll->mode_mask << shift;  in rk3036_pll_get_rate()
339 	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))  in rk3036_pll_get_rate()
349 		con = readl(base + pll->con_offset);  in rk3036_pll_get_rate()
354 		con = readl(base + pll->con_offset + 0x4);  in rk3036_pll_get_rate()
361 		con = readl(base + pll->con_offset + 0x8);  in rk3036_pll_get_rate()
401 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,  in rk3588_pll_set_rate()  argument
407 	rate = rockchip_get_pll_settings(pll, drate);  in rk3588_pll_set_rate()
417 	 * When power on or changing PLL setting,  in rk3588_pll_set_rate()
418 	 * we must force PLL into slow mode to ensure output stable clock.  in rk3588_pll_set_rate()
423 	rk_clrsetreg(base + pll->mode_offset,  in rk3588_pll_set_rate()
424 		     pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
425 		     RKCLK_PLL_MODE_SLOW << pll->mode_shift);  in rk3588_pll_set_rate()
428 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
432 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
436 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
440 	rk_setreg(base + pll->con_offset + RK3588_PLLCON(1),  in rk3588_pll_set_rate()
443 	rk_clrsetreg(base + pll->con_offset,  in rk3588_pll_set_rate()
446 	rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1),  in rk3588_pll_set_rate()
452 		rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),  in rk3588_pll_set_rate()
457 	rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),  in rk3588_pll_set_rate()
460 	/* waiting for pll lock */  in rk3588_pll_set_rate()
461 	while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) &  in rk3588_pll_set_rate()
464 		debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id);  in rk3588_pll_set_rate()
467 	rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
468 		     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);  in rk3588_pll_set_rate()
471 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
481 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
491 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
510 	debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",  in rk3588_pll_set_rate()
511 	      pll, readl(base + pll->con_offset),  in rk3588_pll_set_rate()
512 	      readl(base + pll->con_offset + 0x4),  in rk3588_pll_set_rate()
513 	      readl(base + pll->con_offset + 0x8),  in rk3588_pll_set_rate()
514 	      readl(base + pll->mode_offset));  in rk3588_pll_set_rate()
519 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll,  in rk3588_pll_get_rate()  argument
526 	con = readl(base + pll->mode_offset);  in rk3588_pll_get_rate()
527 	shift = pll->mode_shift;  in rk3588_pll_get_rate()
531 		mode = (con & (pll->mode_mask << shift)) >> shift;  in rk3588_pll_get_rate()
537 		con = readl(base + pll->con_offset);  in rk3588_pll_get_rate()
540 		con = readl(base + pll->con_offset + RK3588_PLLCON(1));  in rk3588_pll_get_rate()
545 		con = readl(base + pll->con_offset + RK3588_PLLCON(2));  in rk3588_pll_get_rate()
567 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,  in rockchip_pll_get_rate()  argument
573 	switch (pll->type) {  in rockchip_pll_get_rate()
575 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
576 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
579 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_get_rate()
580 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
583 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
584 		rate = rk3588_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
587 		printf("%s: Unknown pll type for pll clk %ld\n",  in rockchip_pll_get_rate()
593 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,  in rockchip_pll_set_rate()  argument
599 	if (rockchip_pll_get_rate(pll, base, pll_id) == drate)  in rockchip_pll_set_rate()
602 	switch (pll->type) {  in rockchip_pll_set_rate()
604 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()
605 		ret = rk3036_pll_set_rate(pll, base, pll_id, drate);  in rockchip_pll_set_rate()
608 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_set_rate()
609 		ret = rk3036_pll_set_rate(pll, base, pll_id, drate);  in rockchip_pll_set_rate()
612 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()
613 		ret = rk3588_pll_set_rate(pll, base, pll_id, drate);  in rockchip_pll_set_rate()
616 		printf("%s: Unknown pll type for pll clk %ld\n",  in rockchip_pll_set_rate()