116 	void __iomem *port_mmio = uc_priv->port[port].port_mmio;  in ahci_link_up()  local
124 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_link_up()
136 static void sunxi_dma_init(void __iomem *port_mmio)  in sunxi_dma_init()  argument
138 	clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);  in sunxi_dma_init()
184 	void __iomem *port_mmio;  in ahci_host_init()  local
236 		uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);  in ahci_host_init()
237 		port_mmio = (u8 *)uc_priv->port[i].port_mmio;  in ahci_host_init()
240 		tmp = readl(port_mmio + PORT_CMD);  in ahci_host_init()
246 			writel_with_flush(tmp, port_mmio + PORT_CMD);  in ahci_host_init()
255 		sunxi_dma_init(port_mmio);  in ahci_host_init()
261 		cmd = readl(port_mmio + PORT_CMD);  in ahci_host_init()
263 		writel_with_flush(cmd, port_mmio + PORT_CMD);  in ahci_host_init()
275 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
277 			writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
283 			tmp = readl(port_mmio + PORT_TFDATA);  in ahci_host_init()
287 			tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
294 		tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;  in ahci_host_init()
307 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
309 		writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
312 		tmp = readl(port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
315 			writel(tmp, port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
320 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
544 static int wait_spinup(void __iomem *port_mmio)  in wait_spinup()  argument
551 		tf_data = readl(port_mmio + PORT_TFDATA);  in wait_spinup()
562 	void __iomem *port_mmio = pp->port_mmio;  in ahci_port_start()  local
568 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_port_start()
610 	writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);  in ahci_port_start()
611 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);  in ahci_port_start()
613 	writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);  in ahci_port_start()
614 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);  in ahci_port_start()
617 	sunxi_dma_init(port_mmio);  in ahci_port_start()
622 			  PORT_CMD_START, port_mmio + PORT_CMD);  in ahci_port_start()
630 	return wait_spinup(port_mmio);  in ahci_port_start()
639 	void __iomem *port_mmio = pp->port_mmio;  in ahci_device_data_io()  local
651 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_device_data_io()
666 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ahci_device_data_io()
668 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ahci_device_data_io()
1118 	void __iomem *port_mmio = pp->port_mmio;  in ata_io_flush()  local
1130 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ata_io_flush()
1132 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ata_io_flush()