Lines Matching refs:PCI_SIZE_16

37 	case PCI_SIZE_16:  in pci_byte_size()
138 	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
139 	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
140 	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
141 	{ "status register", PCI_SIZE_16, PCI_STATUS },
164 	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
165 	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
182 	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
183 	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
184 	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
185 	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
186 	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
189 	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
190 	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
194 	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
200 	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
209 	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
210 	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
211 	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
212 	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
213 	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
214 	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
215 	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
216 	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
219 	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
220 	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
221 	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
279 	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);  in pci_header_show_brief()
280 	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);  in pci_header_show_brief()