19 #define FIREWALL_DDR_BASE		0xfe030000
20 #define FW_DDR_MST5_REG			0x54
21 #define FW_DDR_MST13_REG		0x74
22 #define FW_DDR_MST19_REG		0x8c
23 #define FW_DDR_MST21_REG		0x94
24 #define FW_DDR_MST26_REG		0xa8
25 #define FW_DDR_MST27_REG		0xac
26 #define FIREWALL_SYSMEM_BASE		0xfe038000
27 #define FW_SYSM_MST5_REG		0x54
28 #define FW_SYSM_MST13_REG		0x74
29 #define FW_SYSM_MST19_REG		0x8c
30 #define FW_SYSM_MST21_REG		0x94
31 #define FW_SYSM_MST26_REG		0xa8
32 #define FW_SYSM_MST27_REG		0xac
33 #define PMU1_SGRF_BASE			0xfd582000
34 #define PMU1_SGRF_SOC_CON0		0x0
35 #define PMU1_SGRF_SOC_CON6		0x18
36 #define PMU1_SGRF_SOC_CON7		0x1c
37 #define PMU1_SGRF_SOC_CON8		0x20
38 #define PMU1_SGRF_SOC_CON9		0x24
39 #define PMU1_SGRF_SOC_CON10		0x28
40 #define PMU1_SGRF_SOC_CON13		0x34
41 #define SYS_GRF_BASE			0xfd58c000
42 #define SYS_GRF_SOC_CON6		0x0318
43 #define USBGRF_BASE			0xfd5ac000
44 #define USB_GRF_USB3OTG0_CON1		0x001c
45 #define BUS_SGRF_BASE			0xfd586000
46 #define BUS_SGRF_SOC_CON2		0x08
47 #define BUS_SGRF_FIREWALL_CON18		0x288
48 #define PMU_BASE			0xfd8d0000
49 #define PMU_PWR_GATE_SFTCON1		0x8150
51 #define USB2PHY1_GRF_BASE		0xfd5d4000
52 #define USB2PHY2_GRF_BASE		0xfd5d8000
53 #define USB2PHY3_GRF_BASE		0xfd5dc000
54 #define USB2PHY_GRF_CON2		0x0008
56 #define PMU1_IOC_BASE			0xfd5f0000
57 #define PMU2_IOC_BASE			0xfd5f4000
59 #define BUS_IOC_BASE			0xfd5f8000
60 #define BUS_IOC_GPIO2A_IOMUX_SEL_L	0x40
61 #define BUS_IOC_GPIO2B_IOMUX_SEL_L	0x48
62 #define BUS_IOC_GPIO2D_IOMUX_SEL_L	0x58
63 #define BUS_IOC_GPIO2D_IOMUX_SEL_H	0x5c
64 #define BUS_IOC_GPIO3A_IOMUX_SEL_L	0x60
66 #define VCCIO3_5_IOC_BASE		0xfd5fa000
67 #define IOC_VCCIO3_5_GPIO2A_DS_H	0x44
68 #define IOC_VCCIO3_5_GPIO2B_DS_L	0x48
69 #define IOC_VCCIO3_5_GPIO2B_DS_H	0x4c
70 #define IOC_VCCIO3_5_GPIO3A_DS_L	0x60
71 #define IOC_VCCIO3_5_GPIO3A_DS_H	0x64
72 #define IOC_VCCIO3_5_GPIO3C_DS_H	0x74
74 #define EMMC_IOC_BASE			0xfd5fd000
75 #define EMMC_IOC_GPIO2A_DS_L		0x40
76 #define EMMC_IOC_GPIO2D_DS_L		0x58
77 #define EMMC_IOC_GPIO2D_DS_H		0x5c
79 #define CRU_BASE			0xfd7c0000
80 #define CRU_GPLL_CON1			0x01c4
81 #define CRU_SOFTRST_CON77		0x0b34
82 #define CRU_GLB_RST_CON			0x0c10
84 #define PMU1CRU_BASE			0xfd7f0000
85 #define PMU1CRU_SOFTRST_CON00		0x0a00
86 #define PMU1CRU_SOFTRST_CON03		0x0a0c
87 #define PMU1CRU_SOFTRST_CON04		0x0a10
90 #define RK3588_PHY_CONFIG		0xfdee00c0
92 #define VOP_M0_PRIORITY_REG		0xfdf82008
93 #define VOP_M1_PRIORITY_REG		0xfdf82208
101 		.virt = 0x0UL,
102 		.phys = 0x0UL,
103 		.size = 0xf0000000UL,
107 		.virt = 0xf0000000UL,
108 		.phys = 0xf0000000UL,
109 		.size = 0x10000000UL,
114 		.virt = 0x900000000,
115 		.phys = 0x900000000,
116 		.size = 0x150000000,
122 		0,
131 	GPIO0B0_SHIFT		= 0,
132 	GPIO0B0_MASK		= GENMASK(3, 0),
142 	GPIO0C4_SHIFT		= 0,
143 	GPIO0C4_MASK		= GENMASK(3, 0),
179 	GPIO1A0_SHIFT		= 0,
180 	GPIO1A0_MASK		= GENMASK(3, 0),
201 	GPIO1B4_SHIFT		= 0,
202 	GPIO1B4_MASK		= GENMASK(3, 0),
220 	GPIO1C0_SHIFT		= 0,
221 	GPIO1C0_MASK		= GENMASK(3, 0),
231 	GPIO1D0_SHIFT		= 0,
232 	GPIO1D0_MASK		= GENMASK(3, 0),
261 	GPIO2B4_SHIFT		= 0,
262 	GPIO2B4_MASK		= GENMASK(3, 0),
287 	GPIO2C4_SHIFT		= 0,
288 	GPIO2C4_MASK		= GENMASK(3, 0),
294 	GPIO2D4_SHIFT		= 0,
295 	GPIO2D4_MASK		= GENMASK(3, 0),
338 	GPIO3C0_SHIFT		= 0,
339 	GPIO3C0_MASK		= GENMASK(3, 0),
349 	GPIO3C4_SHIFT		= 0,
350 	GPIO3C4_MASK		= GENMASK(3, 0),
360 	GPIO3D0_SHIFT		= 0,
361 	GPIO3D0_MASK		= GENMASK(3, 0),
371 	GPIO3D4_SHIFT		= 0,
372 	GPIO3D4_MASK		= GENMASK(3, 0),
389 	GPIO4A4_SHIFT		= 0,
390 	GPIO4A4_MASK		= GENMASK(3, 0),
404 	GPIO4B0_SHIFT		= 0,
405 	GPIO4B0_MASK		= GENMASK(3, 0),
415 	GPIO4B4_SHIFT		= 0,
416 	GPIO4B4_MASK		= GENMASK(3, 0),
426 	GPIO4D0_SHIFT		= 0,
427 	GPIO4D0_MASK		= GENMASK(3, 0),
428 	GPIO4D0_GPIO		= 0,
438 	GPIO4D1_GPIO		= 0,
449 	GPIO4D4_SHIFT		= 0,
450 	GPIO4D4_MASK		= GENMASK(3, 0),
462 /* UART 0 */  in board_debug_uart_init()
463 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfd890000)  in board_debug_uart_init()
466 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
499 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb40000)  in board_debug_uart_init()
501 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
538 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb50000)  in board_debug_uart_init()
540 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
577 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb60000)  in board_debug_uart_init()
579 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
608 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb70000)  in board_debug_uart_init()
610 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
639 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb80000)  in board_debug_uart_init()
641 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
670 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb90000)  in board_debug_uart_init()
672 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
701 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeba0000)  in board_debug_uart_init()
703 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
732 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebb0000)  in board_debug_uart_init()
734 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
754 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebc0000)  in board_debug_uart_init()
756 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
795 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);  in rockchip_stimer_init()
797 	if (reg & 0x1)  in rockchip_stimer_init()
800 	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));  in rockchip_stimer_init()
801 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);  in rockchip_stimer_init()
802 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);  in rockchip_stimer_init()
803 	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);  in rockchip_stimer_init()
806 static u32 gpio4d_iomux_sel_l = 0xffffffff;
822 	int ret = 0;  in spl_board_storages_fixup()
827 	if (loader->boot_device == BOOT_DEVICE_MMC2 && gpio4d_iomux_sel_l != 0xffffffff) {  in spl_board_storages_fixup()
837 		no_card = mmc_getcd(mmc) == 0;  in spl_board_storages_fixup()
839 			writel(0xffffuL << 16 | gpio4d_iomux_sel_l, &bus_ioc->gpio4d_iomux_sel_l);  in spl_board_storages_fixup()
840 			writel(0xffffuL << 16 | gpio4d_iomux_sel_h, &bus_ioc->gpio4d_iomux_sel_h);  in spl_board_storages_fixup()
841 			writel(0xffffuL << 16 | gpio0a_iomux_sel_h, &pmu1_ioc->gpio0a_iomux_sel_h);  in spl_board_storages_fixup()
855 	secure_reg &= 0xffff;  in arch_cpu_init()
858 	secure_reg &= 0xffff;  in arch_cpu_init()
861 	secure_reg &= 0xffff;  in arch_cpu_init()
864 	secure_reg &= 0xffff;  in arch_cpu_init()
867 	secure_reg &= 0xffff0000;  in arch_cpu_init()
871 	secure_reg &= 0xffff;  in arch_cpu_init()
874 	secure_reg &= 0xffff;  in arch_cpu_init()
877 	secure_reg &= 0xffff;  in arch_cpu_init()
880 	secure_reg &= 0xffff;  in arch_cpu_init()
883 	secure_reg &= 0xffff0000;  in arch_cpu_init()
894 	writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);  in arch_cpu_init()
896 	if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {  in arch_cpu_init()
898 		writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);  in arch_cpu_init()
899 		writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);  in arch_cpu_init()
900 		writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);  in arch_cpu_init()
901 	} else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x1111) {  in arch_cpu_init()
907 		writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);  in arch_cpu_init()
908 		writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);  in arch_cpu_init()
909 		writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);  in arch_cpu_init()
910 	} else if ((readl(BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L) & 0xf0ff) == 0x3033) {  in arch_cpu_init()
912 		writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);  in arch_cpu_init()
913 		writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);  in arch_cpu_init()
914 		writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);  in arch_cpu_init()
915 	} else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L) == 0x5555) {  in arch_cpu_init()
917 		writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);  in arch_cpu_init()
918 		writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);  in arch_cpu_init()
919 		writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);  in arch_cpu_init()
926 	writel(0x01c001c0, CRU_BASE + CRU_SOFTRST_CON77);  in arch_cpu_init()
933 	writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON2);  in arch_cpu_init()
934 	writel(0x20002000, USB2PHY2_GRF_BASE + USB2PHY_GRF_CON2);  in arch_cpu_init()
935 	writel(0x20002000, USB2PHY3_GRF_BASE + USB2PHY_GRF_CON2);  in arch_cpu_init()
938 	writel(0xb800b800, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON03);  in arch_cpu_init()
939 	writel(0x00030003, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON04);  in arch_cpu_init()
946 	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);  in arch_cpu_init()
947 	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);  in arch_cpu_init()
948 	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);  in arch_cpu_init()
951 	 * set VOP M0 and VOP M1 to priority 0x303,then  in arch_cpu_init()
960 	/* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */  in arch_cpu_init()
961 	writel(0x00080008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);  in arch_cpu_init()
963 	return 0;  in arch_cpu_init()
990 		if (map1 > 0) {  in fdt_rm_cooling_map()
997 					pp[0] = cpu_to_fdt32(cpub1_phd);  in fdt_rm_cooling_map()
1006 		if (map2 > 0) {  in fdt_rm_cooling_map()
1013 					pp[0] = cpu_to_fdt32(cpub3_phd);  in fdt_rm_cooling_map()
1028 	if (arm_pmu > 0) {  in fdt_rm_cpu_affinity()
1033 		for (i = 0, remain = 0; i < 8; i++) {  in fdt_rm_cpu_affinity()
1036 				debug("new_aff: 0x%08x\n", (u32)aff[i]);  in fdt_rm_cpu_affinity()
1047 		"cpu@0", "cpu@100", "cpu@200", "cpu@300",  in fdt_rm_cpu()
1060 	if (root_cpus < 0)  in fdt_rm_cpu()
1063 	for (i = 0; i < 8; i++) {  in fdt_rm_cpu()
1074 		if (cluster < 0)  in fdt_rm_cpu()
1082 		if (cpu > 0)  in fdt_rm_cpu()
1086 		if (cpu > 0)  in fdt_rm_cpu()
1102 		if (fdt_path_offset(blob, "/cpus/cpu-map/cluster1") < 0)  in fdt_rm_cpu()
1164 	if (!BAD_RKVENC(mask, 0) && !BAD_RKVENC(mask, 1)) {  in fdt_rm_rkvenc01()
1170 		if (BAD_RKVENC(mask, 0)) {  in fdt_rm_rkvenc01()
1209 	debug("# chip: rk%02x%02x\n", chip_id[0], chip_id[1]);  in fdt_fixup_modules()
1212 	if (!(chip_id[0] == 0x35 && chip_id[1] == 0x82))  in fdt_fixup_modules()
1213 		return 0;  in fdt_fixup_modules()
1221 	/* ip_state[0]: bit0~7 */  in fdt_fixup_modules()
1222 	cpu_mask = ip_state[0];  in fdt_fixup_modules()
1224 	rkvenc_mask = (ip_state[2] & 0x1) | ((ip_state[2] & 0x4) >> 1);  in fdt_fixup_modules()
1225 #if 0  in fdt_fixup_modules()
1227 	gpu_mask = (ip_state[1] & 0x1e) >> 1;  in fdt_fixup_modules()
1229 	rkvdec_mask = (ip_state[1] & 0xc0) >> 6;  in fdt_fixup_modules()
1232 	debug("hwmask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);  in fdt_fixup_modules()
1233 	debug("swmask: 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask);  in fdt_fixup_modules()
1253 	return 0;  in fdt_fixup_modules()
1267 	if (node >= 0) {  in rk_board_fdt_fixup()
1268 		if (fdtdec_get_int(blob, node, "low-power-mode", 0)) {  in rk_board_fdt_fixup()
1270 			writel(0x00000100, RK3588_PHY_CONFIG);  in rk_board_fdt_fixup()
1274 	return 0;  in rk_board_fdt_fixup()
1284 	writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);  in spl_fit_standalone_release()
1287 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);  in spl_fit_standalone_release()
1290 	writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);  in spl_fit_standalone_release()
1292 	writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);  in spl_fit_standalone_release()
1294 	writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);  in spl_fit_standalone_release()
1296 	writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);  in spl_fit_standalone_release()
1298 	writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);  in spl_fit_standalone_release()
1300 	/* 0xf0000000 ~ 0xfee00000 */  in spl_fit_standalone_release()
1301 	writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);  in spl_fit_standalone_release()
1302 	writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);  in spl_fit_standalone_release()
1303 	writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);  in spl_fit_standalone_release()
1305 	writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);  in spl_fit_standalone_release()
1307 	writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);  in spl_fit_standalone_release()
1309 	/* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */  in spl_fit_standalone_release()
1311 	return 0;  in spl_fit_standalone_release()