Lines Matching refs:pctl
31 struct rk3288_ddr_pctl *pctl; member
175 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
177 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
179 &pctl->dfistcfg1); in dfi_cfg()
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
182 &pctl->dfilpcfg0); in dfi_cfg()
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
188 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
189 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
193 &pctl->dfiodtcfg); in dfi_cfg()
195 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
197 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
219 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
223 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
229 &pctl->dfitrddataen); in pctl_cfg()
232 &pctl->dfitrddataen); in pctl_cfg()
235 &pctl->dfitphywrlat); in pctl_cfg()
239 &pctl->mcfg); in pctl_cfg()
244 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
301 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
304 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
306 while (readl(&pctl->mcmd) & START_CMD) in send_command()
310 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, in send_command_op() argument
313 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
331 struct rk3288_ddr_pctl *pctl) in move_to_config_state() argument
336 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
340 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
341 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
356 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
357 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
371 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio() local
376 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
385 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
401 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
413 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training() local
416 writel(0, &pctl->trefi); in data_training()
440 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
456 send_command(pctl, rank, REF_CMD, 0); in data_training()
462 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
470 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state() local
474 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
478 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
482 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
483 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
491 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
492 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
496 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
497 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
621 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect() local
644 move_to_config_state(publ, pctl); in sdram_col_row_detect()
713 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init() local
719 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
721 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
727 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
728 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
732 move_to_config_state(publ, pctl); in sdram_init()
761 writel(0, &pctl->mrrcfg0); in sdram_init()
763 send_command_op(pctl, 1, MRR_CMD, i, 0); in sdram_init()
885 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3066_dmc_probe()