Lines Matching +full:opp +full:- +full:450000000
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rv1126-cru.h>
7 #include <dt-bindings/power/rv1126-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rv1126.h>
15 #include "rv1126-dram-default-timing.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
23 interrupt-parent = <&gic>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a7";
52 enable-method = "psci";
54 operating-points-v2 = <&cpu0_opp_table>;
55 cpu-idle-states = <&CPU_SLEEP>;
60 compatible = "arm,cortex-a7";
62 enable-method = "psci";
64 operating-points-v2 = <&cpu0_opp_table>;
65 cpu-idle-states = <&CPU_SLEEP>;
70 compatible = "arm,cortex-a7";
72 enable-method = "psci";
74 operating-points-v2 = <&cpu0_opp_table>;
75 cpu-idle-states = <&CPU_SLEEP>;
80 compatible = "arm,cortex-a7";
82 enable-method = "psci";
84 operating-points-v2 = <&cpu0_opp_table>;
85 cpu-idle-states = <&CPU_SLEEP>;
88 idle-states {
89 entry-method = "psci";
91 CPU_SLEEP: cpu-sleep {
92 compatible = "arm,idle-state";
93 local-timer-stop;
94 arm,psci-suspend-param = <0x0010000>;
95 entry-latency-us = <120>;
96 exit-latency-us = <250>;
97 min-residency-us = <900>;
103 cpu0_opp_table: cpu0-opp-table {
104 compatible = "operating-points-v2";
105 opp-shared;
106 rockchip,reboot-freq = <816000>;
108 opp-408000000 {
109 opp-hz = /bits/ 64 <408000000>;
110 opp-microvolt = <725000 725000 1100000>;
111 clock-latency-ns = <40000>;
113 opp-600000000 {
114 opp-hz = /bits/ 64 <600000000>;
115 opp-microvolt = <725000 725000 1000000>;
116 clock-latency-ns = <40000>;
118 opp-816000000 {
119 opp-hz = /bits/ 64 <816000000>;
120 opp-microvolt = <725000 725000 1000000>;
121 clock-latency-ns = <40000>;
122 opp-suspend;
124 opp-1008000000 {
125 opp-hz = /bits/ 64 <1008000000>;
126 opp-microvolt = <775000 775000 1000000>;
127 clock-latency-ns = <40000>;
129 opp-1200000000 {
130 opp-hz = /bits/ 64 <1200000000>;
131 opp-microvolt = <825000 825000 1000000>;
132 clock-latency-ns = <40000>;
134 opp-1296000000 {
135 opp-hz = /bits/ 64 <1296000000>;
136 opp-microvolt = <875000 875000 1000000>;
137 clock-latency-ns = <40000>;
139 opp-1416000000 {
140 opp-hz = /bits/ 64 <1416000000>;
141 opp-microvolt = <925000 925000 1000000>;
142 clock-latency-ns = <40000>;
144 opp-1512000000 {
145 opp-hz = /bits/ 64 <1512000000>;
146 opp-microvolt = <975000 975000 1000000>;
147 clock-latency-ns = <40000>;
151 arm-pmu {
152 compatible = "arm,cortex-a7-pmu";
157 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
160 bus_soc: bus-soc {
161 compatible = "rockchip,rv1126-bus";
162 rockchip,busfreq-policy = "smc";
163 soc-bus0 {
164 bus-id = <0>;
165 cfg-val = <0x00300020>;
166 enable-msk = <0x7144>;
169 soc-bus1 {
170 bus-id = <1>;
171 cfg-val = <0x00300020>;
172 enable-msk = <0x70ff>;
175 soc-bus2 {
176 bus-id = <2>;
177 cfg-val = <0x00300020>;
178 enable-msk = <0x70ff>;
181 soc-bus3 {
182 bus-id = <3>;
183 cfg-val = <0x00300020>;
184 enable-msk = <0x70ff>;
187 soc-bus4 {
188 bus-id = <4>;
189 cfg-val = <0x00300020>;
190 enable-msk = <0x7011>;
193 soc-bus5 {
194 bus-id = <5>;
195 cfg-val = <0x00300020>;
196 enable-msk = <0x7011>;
199 soc-bus6 {
200 bus-id = <6>;
201 cfg-val = <0x00300020>;
202 enable-msk = <0x7011>;
205 soc-bus7 {
206 bus-id = <7>;
207 cfg-val = <0x00300020>;
208 enable-msk = <0x0>;
211 soc-bus8 {
212 bus-id = <8>;
213 cfg-val = <0x00300020>;
214 enable-msk = <0x0>;
217 soc-bus9 {
218 bus-id = <9>;
219 cfg-val = <0x00300020>;
220 enable-msk = <0x0>;
223 soc-bus10 {
224 bus-id = <10>;
225 cfg-val = <0x00300020>;
226 enable-msk = <0x0>;
229 soc-bus11 {
230 bus-id = <11>;
231 cfg-val = <0x00300020>;
232 enable-msk = <0x7000>;
237 display_subsystem: display-subsystem {
238 compatible = "rockchip,display-subsystem";
243 route_dsi: route-dsi {
252 route_rgb: route-rgb {
263 fiq_debugger: fiq-debugger {
264 compatible = "rockchip,fiq-debugger";
265 rockchip,serial-id = <2>;
266 rockchip,wake-irq = <0>;
267 rockchip,irq-mode-enable = <0>;
275 compatible = "linaro,optee-tz";
281 mpp_srv: mpp-srv {
282 compatible = "rockchip,mpp-service";
283 rockchip,taskqueue-count = <3>;
284 rockchip,resetgroup-count = <3>;
289 compatible = "arm,psci-1.0";
293 reserved-memory {
294 #address-cells = <1>;
295 #size-cells = <1>;
299 compatible = "shared-dma-pool";
307 record-size = <0x20000>;
308 console-size = <0x40000>;
309 ftrace-size = <0x00000>;
310 pmsg-size = <0x40000>;
315 rockchip_suspend: rockchip-suspend {
316 compatible = "rockchip,pm-rv1126";
318 rockchip,sleep-debug-en = <0>;
319 rockchip,sleep-mode-config = <
327 rockchip,wakeup-config = <
334 rockchip_system_monitor: rockchip-system-monitor {
335 compatible = "rockchip,system-monitor";
338 thermal_zones: thermal-zones {
339 cpu_thermal: cpu-thermal {
340 polling-delay-passive = <20>; /* milliseconds */
341 polling-delay = <1000>; /* milliseconds */
342 sustainable-power = <977>; /* milliwatts */
344 thermal-sensors = <&cpu_tsadc 0>;
347 npu_thermal: npu-thermal {
348 polling-delay-passive = <20>; /* milliseconds */
349 polling-delay = <1000>; /* milliseconds */
350 sustainable-power = <977>; /* milliwatts */
352 thermal-sensors = <&npu_tsadc 0>;
357 compatible = "arm,armv7-timer";
362 clock-frequency = <24000000>;
366 compatible = "fixed-clock";
367 clock-frequency = <24000000>;
368 clock-output-names = "xin24m";
369 #clock-cells = <0>;
372 gmac_clkin_m0: external-gmac-clockm0 {
373 compatible = "fixed-clock";
374 clock-frequency = <125000000>;
375 clock-output-names = "clk_gmac_rgmii_clkin_m0";
376 #clock-cells = <0>;
379 gmac_clkini_m1: external-gmac-clockm1 {
380 compatible = "fixed-clock";
381 clock-frequency = <125000000>;
382 clock-output-names = "clk_gmac_rgmii_clkin_m1";
383 #clock-cells = <0>;
387 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
391 compatible = "rockchip,rv1126-rgb";
395 #address-cells = <1>;
396 #size-cells = <0>;
400 #address-cells = <1>;
401 #size-cells = <0>;
405 remote-endpoint = <&vop_out_rgb>;
414 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
417 pmu_io_domains: io-domains {
418 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
421 reboot-mode {
422 compatible = "syscon-reboot-mode";
424 mode-bootloader = <BOOT_BL_DOWNLOAD>;
425 mode-charge = <BOOT_CHARGING>;
426 mode-fastboot = <BOOT_FASTBOOT>;
427 mode-loader = <BOOT_BL_DOWNLOAD>;
428 mode-normal = <BOOT_NORMAL>;
429 mode-recovery = <BOOT_RECOVERY>;
430 mode-ums = <BOOT_UMS>;
544 gic: interrupt-controller@feff0000 {
545 compatible = "arm,gic-400";
546 interrupt-controller;
547 #interrupt-cells = <3>;
548 #address-cells = <0>;
557 arm-debug@ff010000 {
566 compatible = "rockchip,rv1126-cpu-pvtm";
568 #address-cells = <1>;
569 #size-cells = <0>;
574 clock-names = "clk", "pclk";
576 reset-names = "rst", "rst-p";
580 pmu: power-management@ff3e0000 {
581 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
584 power: power-controller {
585 compatible = "rockchip,rv1126-power-controller";
586 #power-domain-cells = <1>;
587 #address-cells = <1>;
588 #size-cells = <0>;
705 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
708 #address-cells = <1>;
709 #size-cells = <0>;
711 clock-names = "i2c", "pclk";
712 pinctrl-names = "default";
713 pinctrl-0 = <&i2c0_xfer>;
718 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
721 #address-cells = <1>;
722 #size-cells = <0>;
725 clock-names = "i2c", "pclk";
726 pinctrl-names = "default";
727 pinctrl-0 = <&i2c2_xfer>;
732 compatible = "simple-bus";
733 #address-cells = <1>;
734 #size-cells = <1>;
737 dmac: dma-controller@ff4e0000 {
742 #dma-cells = <1>;
744 clock-names = "apb_pclk";
749 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
752 reg-shift = <2>;
753 reg-io-width = <4>;
755 clock-frequency = <24000000>;
757 clock-names = "baudclk", "apb_pclk";
758 pinctrl-names = "default";
759 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
764 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
766 #pwm-cells = <3>;
767 pinctrl-names = "active";
768 pinctrl-0 = <&pwm0m0_pins>;
770 clock-names = "pwm", "pclk";
775 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
777 #pwm-cells = <3>;
778 pinctrl-names = "active";
779 pinctrl-0 = <&pwm1m0_pins>;
781 clock-names = "pwm", "pclk";
786 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
788 #pwm-cells = <3>;
789 pinctrl-names = "active";
790 pinctrl-0 = <&pwm2m0_pins>;
792 clock-names = "pwm", "pclk";
797 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
799 #pwm-cells = <3>;
800 pinctrl-names = "active";
801 pinctrl-0 = <&pwm3m0_pins>;
803 clock-names = "pwm", "pclk";
808 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
810 #pwm-cells = <3>;
811 pinctrl-names = "active";
812 pinctrl-0 = <&pwm4m0_pins>;
814 clock-names = "pwm", "pclk";
819 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
821 #pwm-cells = <3>;
822 pinctrl-names = "active";
823 pinctrl-0 = <&pwm5m0_pins>;
825 clock-names = "pwm", "pclk";
830 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
832 #pwm-cells = <3>;
833 pinctrl-names = "active";
834 pinctrl-0 = <&pwm6m0_pins>;
836 clock-names = "pwm", "pclk";
841 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
843 #pwm-cells = <3>;
844 pinctrl-names = "active";
845 pinctrl-0 = <&pwm7m0_pins>;
847 clock-names = "pwm", "pclk";
852 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
855 #address-cells = <1>;
856 #size-cells = <0>;
858 clock-names = "spiclk", "apb_pclk";
860 dma-names = "tx", "rx";
861 pinctrl-names = "default", "high_speed";
862 pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>;
863 pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>;
868 compatible = "rockchip,rv1126-pmu-pvtm";
870 #address-cells = <1>;
871 #size-cells = <0>;
876 clock-names = "clk", "pclk";
879 reset-names = "rst", "rst-p";
883 pmucru: clock-controller@ff480000 {
884 compatible = "rockchip,rv1126-pmucru";
887 #clock-cells = <1>;
888 #reset-cells = <1>;
891 cru: clock-controller@ff490000 {
892 compatible = "rockchip,rv1126-cru";
895 #clock-cells = <1>;
896 #reset-cells = <1>;
898 assigned-clocks =
906 assigned-clock-rates =
914 assigned-clock-parents =
918 csi_dphy0: csi-dphy@ff4b0000 {
919 compatible = "rockchip,rv1126-csi-dphy";
922 clock-names = "pclk";
927 csi_dphy1: csi-dphy@ff4b8000 {
928 compatible = "rockchip,rv1126-csi-dphy";
931 clock-names = "pclk";
936 u2phy0: usb2-phy@ff4c0000 {
937 compatible = "rockchip,rv1126-usb2phy";
941 clock-names = "phyclk", "pclk";
943 reset-names = "u2phy", "u2phy-apb";
944 #clock-cells = <0>;
947 u2phy_otg: otg-port {
948 #phy-cells = <0>;
953 interrupt-names = "otg-bvalid", "otg-id",
959 u2phy1: usb2-phy@ff4c8000 {
960 compatible = "rockchip,rv1126-usb2phy";
964 clock-names = "phyclk", "pclk";
965 assigned-clocks = <&cru USB480M>;
966 assigned-clock-parents = <&u2phy1>;
968 reset-names = "u2phy", "u2phy-apb";
969 #clock-cells = <0>;
970 clock-output-names = "usb480m_phy";
973 u2phy_host: host-port {
974 #phy-cells = <0>;
977 interrupt-names = "linestate", "disconnect";
982 mipi_dphy: mipi-dphy@ff4d0000 {
983 compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy";
985 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
986 assigned-clock-rates = <24000000>;
988 clock-names = "ref", "pclk";
989 clock-output-names = "mipi_dphy_pll";
990 #clock-cells = <0>;
992 reset-names = "apb";
993 #phy-cells = <0>;
999 compatible = "rockchip,rv1126-crypto";
1001 clock-names = "sclk_crypto", "sclk_crypto_apk";
1003 clock-frequency = <200000000>, <300000000>;
1007 compatible = "rockchip,cryptov2-rng";
1013 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1019 clock-names = "i2c", "pclk";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&i2c1_xfer>;
1026 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1032 clock-names = "i2c", "pclk";
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&i2c3m0_xfer>;
1039 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1045 clock-names = "i2c", "pclk";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c4m0_xfer>;
1052 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1058 clock-names = "i2c", "pclk";
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&i2c5m0_xfer>;
1065 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1067 #pwm-cells = <3>;
1068 pinctrl-names = "active";
1069 pinctrl-0 = <&pwm8m0_pins>;
1071 clock-names = "pwm", "pclk";
1076 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1078 #pwm-cells = <3>;
1079 pinctrl-names = "active";
1080 pinctrl-0 = <&pwm9m0_pins>;
1082 clock-names = "pwm", "pclk";
1087 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1089 #pwm-cells = <3>;
1090 pinctrl-names = "active";
1091 pinctrl-0 = <&pwm10m0_pins>;
1093 clock-names = "pwm", "pclk";
1098 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
1100 #pwm-cells = <3>;
1101 pinctrl-names = "active";
1102 pinctrl-0 = <&pwm11m0_pins>;
1104 clock-names = "pwm", "pclk";
1109 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1112 reg-shift = <2>;
1113 reg-io-width = <4>;
1115 clock-frequency = <24000000>;
1117 clock-names = "baudclk", "apb_pclk";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
1124 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1127 reg-shift = <2>;
1128 reg-io-width = <4>;
1130 clock-frequency = <24000000>;
1132 clock-names = "baudclk", "apb_pclk";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&uart2m1_xfer>;
1139 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1142 reg-shift = <2>;
1143 reg-io-width = <4>;
1145 clock-frequency = <24000000>;
1147 clock-names = "baudclk", "apb_pclk";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>;
1154 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1157 reg-shift = <2>;
1158 reg-io-width = <4>;
1160 clock-frequency = <24000000>;
1162 clock-names = "baudclk", "apb_pclk";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
1169 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
1172 reg-shift = <2>;
1173 reg-io-width = <4>;
1175 clock-frequency = <24000000>;
1177 clock-names = "baudclk", "apb_pclk";
1178 pinctrl-names = "default";
1179 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1184 compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1190 clock-names = "spiclk", "apb_pclk";
1192 dma-names = "tx", "rx";
1193 pinctrl-names = "default", "high_speed";
1194 pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>;
1195 pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>;
1200 compatible = "rockchip,rv1126-otp";
1202 #address-cells = <1>;
1203 #size-cells = <1>;
1205 clock-names = "otp", "apb_pclk";
1212 cpu_leakage: cpu-leakage@17 {
1215 logic_leakage: logic-leakage@18 {
1218 npu_leakage: npu-leakage@19 {
1224 compatible = "rockchip,rk3399-saradc";
1227 #io-channel-cells = <1>;
1229 clock-names = "saradc", "apb_pclk";
1231 reset-names = "saradc-apb";
1236 compatible = "rockchip,rv1126-tsadc";
1240 assigned-clocks = <&cru CLK_CPU_TSADC>;
1241 assigned-clock-rates = <4000000>;
1244 clock-names = "tsadc", "apb_pclk", "phy_clk";
1247 reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
1248 rockchip,hw-tshut-temp = <120000>;
1249 #thermal-sensor-cells = <1>;
1254 compatible = "rockchip,rv1126-tsadc";
1258 assigned-clocks = <&cru CLK_NPU_TSADC>;
1259 assigned-clock-rates = <4000000>;
1262 clock-names = "tsadc", "apb_pclk", "phy_clk";
1265 reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
1266 rockchip,hw-tshut-temp = <120000>;
1267 #thermal-sensor-cells = <1>;
1272 compatible = "rockchip,can-1.0";
1275 assigned-clocks = <&cru CLK_CAN>;
1276 assigned-clock-rates = <200000000>;
1278 clock-names = "baudclk", "apb_pclk";
1280 reset-names = "can", "can-apb";
1285 compatible = "rockchip,rk3288-timer";
1289 clock-names = "pclk", "timer";
1293 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
1298 reset-names = "reset";
1303 compatible = "rockchip,rv1126-mailbox",
1304 "rockchip,rk3368-mailbox";
1308 clock-names = "pclk_mailbox";
1309 #mbox-cells = <1>;
1314 compatible = "rockchip,hw-decompress";
1318 clock-names = "aclk", "dclk", "pclk";
1320 reset-names = "dresetn";
1321 data-cached = <0>;
1326 compatible = "rockchip,rv1126-i2s-tdm";
1330 clock-names = "mclk_tx", "mclk_rx", "hclk";
1332 dma-names = "tx", "rx";
1334 reset-names = "tx-m", "rx-m";
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&i2s0m0_sclk_tx
1351 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
1355 clock-names = "i2s_clk", "i2s_hclk";
1357 dma-names = "tx", "rx";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&i2s1m0_sclk
1367 compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
1371 clock-names = "i2s_clk", "i2s_hclk";
1373 dma-names = "tx", "rx";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&i2s2m0_sclk
1383 compatible = "rockchip,rv1126-pdm", "rockchip,pdm";
1386 clock-names = "pdm_clk", "pdm_hclk";
1388 dma-names = "rx";
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&pdmm0_clk
1400 compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1";
1403 clock-names = "clk", "hclk";
1405 dma-names = "tx";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&audpwmm0_pins>;
1408 rockchip,sample-width-bits = <11>;
1409 rockchip,interpolat-points = <1>;
1415 compatible = "rockchip,rv1126-dfi";
1421 compatible = "rockchip,rv1126-dmc";
1422 devfreq-events = <&dfi>;
1424 clock-names = "dmc_clk";
1425 operating-points-v2 = <&dmc_opp_table>;
1429 system-status-freq = <
1439 auto-min-freq = <328000>;
1440 auto-freq-en = <0>;
1441 #cooling-cells = <2>;
1445 dmc_opp_table: dmc-opp-table {
1446 compatible = "operating-points-v2";
1448 opp-328000000 {
1449 opp-hz = /bits/ 64 <328000000>;
1450 opp-microvolt = <800000>;
1452 opp-450000000 {
1453 opp-hz = /bits/ 64 <450000000>;
1454 opp-microvolt = <800000>;
1456 opp-664000000 {
1457 opp-hz = /bits/ 64 <664000000>;
1458 opp-microvolt = <800000>;
1460 opp-924000000 {
1461 opp-hz = /bits/ 64 <924000000>;
1462 opp-microvolt = <800000>;
1464 opp-1056000000 {
1465 opp-hz = /bits/ 64 <1056000000>;
1466 opp-microvolt = <800000>;
1472 compatible = "rockchip,rv1126-cif";
1474 reg-names = "cif_regs";
1476 interrupt-names = "cif-intr";
1480 clock-names = "aclk_cif", "aclk_cif_lite",
1488 reset-names = "rst_cif_a", "rst_cif_h",
1493 assigned-clocks = <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>;
1494 assigned-clock-rates = <300000000>, <300000000>;
1495 power-domains = <&power RV1126_PD_VI>;
1504 interrupt-names = "cif_mmu";
1506 clock-names = "aclk", "hclk";
1507 power-domains = <&power RV1126_PD_VI>;
1508 #iommu-cells = <0>;
1517 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
1518 power-domains = <&power RV1126_PD_VO>;
1519 dma-coherent;
1524 compatible = "rockchip,rv1126-vop";
1526 reg-names = "regs", "gamma_lut";
1530 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1532 power-domains = <&power RV1126_PD_VO>;
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1541 remote-endpoint = <&rgb_in_vop>;
1546 remote-endpoint = <&dsi_in_vop>;
1555 interrupt-names = "vop_mmu";
1557 clock-names = "aclk", "iface";
1558 #iommu-cells = <0>;
1559 rockchip,disable-device-link-resume;
1560 power-domains = <&power RV1126_PD_VO>;
1564 mipi_csi2: mipi-csi2@ffb10000 {
1565 compatible = "rockchip,rv1126-mipi-csi2";
1567 reg-names = "csihost_regs";
1570 interrupt-names = "csi-intr1", "csi-intr2";
1572 clock-names = "pclk_csi2host", "srst_csihost_p";
1573 power-domains = <&power RV1126_PD_VI>;
1578 compatible = "rockchip,rv1126-mipi-dsi";
1582 clock-names = "pclk", "hs_clk";
1584 reset-names = "apb";
1586 phy-names = "mipi_dphy";
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1590 power-domains = <&power RV1126_PD_VO>;
1596 remote-endpoint = <&vop_out_dsi>;
1603 compatible = "rockchip,rv1126-rkisp";
1608 interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
1611 clock-names = "aclk_isp", "hclk_isp", "clk_isp";
1612 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1613 assigned-clock-rates = <500000000>, <250000000>;
1614 power-domains = <&power RV1126_PD_VI>;
1616 memory-region = <&isp_reserved>;
1624 interrupt-names = "isp_mmu";
1626 clock-names = "aclk", "iface";
1627 power-domains = <&power RV1126_PD_VI>;
1628 #iommu-cells = <0>;
1629 rockchip,disable-mmu-reset;
1634 compatible = "rockchip,rv1126-rkispp";
1638 interrupt-names = "ispp_irq", "fec_irq";
1641 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
1642 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
1644 assigned-clock-rates = <500000000>, <250000000>,
1646 power-domains = <&power RV1126_PD_ISPP>;
1657 interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1";
1659 clock-names = "aclk", "iface";
1660 power-domains = <&power RV1126_PD_ISPP>;
1661 #iommu-cells = <0>;
1662 rockchip,disable-mmu-reset;
1667 compatible = "rockchip,rkv-decoder-v1";
1670 interrupt-names = "irq_dec";
1674 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
1679 reset-names = "video_a", "video_h", "video_cabac",
1681 power-domains = <&power RV1126_PD_VDPU>;
1684 rockchip,taskqueue-node = <0>;
1685 rockchip,resetgroup-node = <0>;
1693 interrupt-names = "rkvdec_mmu";
1695 clock-names = "aclk", "iface";
1696 power-domains = <&power RV1126_PD_VDPU>;
1697 #iommu-cells = <0>;
1702 compatible = "rockchip,vpu-encoder-v2";
1706 clock-names = "aclk_vcodec", "hclk_vcodec";
1708 reset-names = "shared_video_a", "shared_video_h";
1711 rockchip,taskqueue-node = <1>;
1712 rockchip,resetgroup-node = <1>;
1713 power-domains = <&power RV1126_PD_VDPU>;
1718 compatible = "rockchip,vpu-decoder-v2";
1721 interrupt-names = "irq_dec";
1723 clock-names = "aclk_vcodec", "hclk_vcodec";
1725 reset-names = "shared_video_a", "shared_video_h";
1727 power-domains = <&power RV1126_PD_VDPU>;
1729 rockchip,taskqueue-node = <1>;
1730 rockchip,resetgroup-node = <1>;
1738 interrupt-names = "vpu_mmu";
1739 clock-names = "aclk", "iface";
1741 power-domains = <&power RV1126_PD_VDPU>;
1742 #iommu-cells = <0>;
1747 compatible = "rockchip,rkv-encoder-v1";
1750 interrupt-names = "irq_enc";
1753 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1756 reset-names = "video_a", "video_h", "video_core";
1757 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>;
1758 assigned-clock-rates = <297000000>, <594000000>;
1759 operating-points-v2 = <&rkvenc_opp_table>;
1761 node-name = "rkvenc";
1763 rockchip,taskqueue-node = <2>;
1764 rockchip,resetgroup-node = <2>;
1765 power-domains = <&power RV1126_PD_VEPU>;
1769 rkvenc_opp_table: rkvenc-opp-table {
1770 compatible = "operating-points-v2";
1773 opp-297000000 {
1774 opp-hz = /bits/ 64 <297000000>;
1775 opp-microvolt = <725000 725000 1000000>;
1777 opp-396000000 {
1778 opp-hz = /bits/ 64 <396000000>;
1779 opp-microvolt = <725000 725000 1000000>;
1781 opp-500000000 {
1782 opp-hz = /bits/ 64 <500000000>;
1783 opp-microvolt = <750000 750000 1000000>;
1785 opp-594000000 {
1786 opp-hz = /bits/ 64 <594000000>;
1787 opp-microvolt = <800000 800000 1000000>;
1796 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
1798 clock-names = "aclk", "iface";
1799 rockchip,disable-mmu-reset;
1800 #iommu-cells = <0>;
1801 power-domains = <&power RV1126_PD_VEPU>;
1806 compatible = "rockchip,rv1126-npu-pvtm";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1814 clock-names = "clk", "pclk";
1816 reset-names = "rts", "rst-p";
1821 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
1825 interrupt-names = "macirq", "eth_wake_irq";
1831 clock-names = "stmmaceth", "mac_clk_rx",
1836 reset-names = "stmmaceth";
1838 snps,mixed-burst;
1841 snps,axi-config = <&stmmac_axi_setup>;
1842 snps,mtl-rx-config = <&mtl_rx_setup>;
1843 snps,mtl-tx-config = <&mtl_tx_setup>;
1847 compatible = "snps,dwmac-mdio";
1848 #address-cells = <0x1>;
1849 #size-cells = <0x0>;
1852 stmmac_axi_setup: stmmac-axi-config {
1858 mtl_rx_setup: rx-queues-config {
1859 snps,rx-queues-to-use = <1>;
1863 mtl_tx_setup: tx-queues-config {
1864 snps,tx-queues-to-use = <1>;
1870 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
1875 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1876 fifo-depth = <0x100>;
1877 max-frequency = <200000000>;
1878 pinctrl-names = "default";
1879 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1880 power-domains = <&power RV1126_PD_NVM>;
1881 rockchip,use-v2-tuning;
1886 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
1891 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1892 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
1893 fifo-depth = <0x100>;
1894 max-frequency = <200000000>;
1895 pinctrl-names = "default";
1896 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1901 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
1906 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1907 fifo-depth = <0x100>;
1908 max-frequency = <200000000>;
1909 pinctrl-names = "default";
1910 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
1911 power-domains = <&power RV1126_PD_SDIO>;
1916 compatible = "rockchip,rk-nandc";
1921 clock-names = "clk_nandc", "hclk_nandc";
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&flash_pins>;
1924 power-domains = <&power RV1126_PD_NVM>;
1933 clock-names = "clk_sfc", "hclk_sfc";
1934 pinctrl-names = "default";
1935 pinctrl-0 = <&flash_pins>;
1936 assigned-clocks = <&cru SCLK_SFC>;
1937 assigned-clock-rates = <80000000>;
1938 power-domains = <&power RV1126_PD_NVM>;
1946 clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu";
1947 assigned-clocks = <&cru CLK_CORE_NPU>;
1948 assigned-clock-rates = <396000000>;
1949 operating-points-v2 = <&npu_opp_table>;
1951 power-domains = <&power RV1126_PD_NPU>;
1955 npu_opp_table: npu-opp-table {
1956 compatible = "operating-points-v2";
1958 opp-200000000 {
1959 opp-hz = /bits/ 64 <200000000>;
1960 opp-microvolt = <725000 725000 1000000>;
1962 opp-300000000 {
1963 opp-hz = /bits/ 64 <300000000>;
1964 opp-microvolt = <725000 725000 1000000>;
1966 opp-396000000 {
1967 opp-hz = /bits/ 64 <396000000>;
1968 opp-microvolt = <725000 725000 1000000>;
1970 opp-500000000 {
1971 opp-hz = /bits/ 64 <500000000>;
1972 opp-microvolt = <725000 725000 1000000>;
1974 opp-600000000 {
1975 opp-hz = /bits/ 64 <600000000>;
1976 opp-microvolt = <725000 725000 1000000>;
1978 opp-700000000 {
1979 opp-hz = /bits/ 64 <700000000>;
1980 opp-microvolt = <775000 775000 1000000>;
1982 opp-800000000 {
1983 opp-hz = /bits/ 64 <800000000>;
1984 opp-microvolt = <825000 825000 1000000>;
1989 compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3";
1990 #address-cells = <1>;
1991 #size-cells = <1>;
1995 clock-names = "ref_clk", "bus_clk", "hclk";
2003 maximum-speed = "high-speed";
2005 phy-names = "usb2-phy";
2007 power-domains = <&power RV1126_PD_USB>;
2009 reset-names = "usb3-otg";
2011 snps,dis-u2-freeclk-exists-quirk;
2013 snps,dis-del-phy-power-chg-quirk;
2014 snps,tx-ipgap-linecheck-dis-quirk;
2015 snps,xhci-trb-ent-quirk;
2021 compatible = "generic-ehci";
2026 clock-names = "usbhost", "arbiter", "utmi";
2028 phy-names = "usb";
2029 power-domains = <&power RV1126_PD_USB>;
2034 compatible = "generic-ohci";
2039 clock-names = "usbhost", "arbiter", "utmi";
2041 phy-names = "usb";
2042 power-domains = <&power RV1126_PD_USB>;
2047 compatible = "rockchip,rv1126-pinctrl";
2050 #address-cells = <1>;
2051 #size-cells = <1>;
2055 compatible = "rockchip,gpio-bank";
2060 gpio-controller;
2061 #gpio-cells = <2>;
2063 interrupt-controller;
2064 #interrupt-cells = <2>;
2068 compatible = "rockchip,gpio-bank";
2073 gpio-controller;
2074 #gpio-cells = <2>;
2076 interrupt-controller;
2077 #interrupt-cells = <2>;
2081 compatible = "rockchip,gpio-bank";
2086 gpio-controller;
2087 #gpio-cells = <2>;
2089 interrupt-controller;
2090 #interrupt-cells = <2>;
2094 compatible = "rockchip,gpio-bank";
2099 gpio-controller;
2100 #gpio-cells = <2>;
2102 interrupt-controller;
2103 #interrupt-cells = <2>;
2107 compatible = "rockchip,gpio-bank";
2112 gpio-controller;
2113 #gpio-cells = <2>;
2115 interrupt-controller;
2116 #interrupt-cells = <2>;
2121 #include "rv1126-pinctrl.dtsi"