Lines Matching full:cru
6 #include <dt-bindings/clock/rv1126-cru.h>
53 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
73 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
573 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
575 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
594 clocks = <&cru ACLK_NPU>,
595 <&cru HCLK_NPU>,
596 <&cru PCLK_PDNPU>,
597 <&cru CLK_CORE_NPU>;
603 clocks = <&cru ACLK_VENC>,
604 <&cru HCLK_VENC>,
605 <&cru CLK_VENC_CORE>;
613 clocks = <&cru ACLK_CRYPTO>,
614 <&cru HCLK_CRYPTO>,
615 <&cru CLK_CRYPTO_CORE>,
616 <&cru CLK_CRYPTO_PKA>;
621 clocks = <&cru ACLK_ISP>,
622 <&cru HCLK_ISP>,
623 <&cru CLK_ISP>,
624 <&cru ACLK_CIF>,
625 <&cru HCLK_CIF>,
626 <&cru DCLK_CIF>,
627 <&cru CLK_CIF_OUT>,
628 <&cru CLK_MIPICSI_OUT>,
629 <&cru PCLK_CSIHOST>,
630 <&cru ACLK_CIFLITE>,
631 <&cru HCLK_CIFLITE>,
632 <&cru DCLK_CIFLITE>;
639 clocks = <&cru ACLK_RGA>,
640 <&cru HCLK_RGA>,
641 <&cru CLK_RGA_CORE>,
642 <&cru ACLK_VOP>,
643 <&cru HCLK_VOP>,
644 <&cru DCLK_VOP>,
645 <&cru PCLK_DSIHOST>,
646 <&cru ACLK_IEP>,
647 <&cru HCLK_IEP>,
648 <&cru CLK_IEP_CORE>;
654 clocks = <&cru ACLK_ISPP>,
655 <&cru HCLK_ISPP>,
656 <&cru CLK_ISPP>;
662 clocks = <&cru ACLK_VDEC>,
663 <&cru HCLK_VDEC>,
664 <&cru CLK_VDEC_CORE>,
665 <&cru CLK_VDEC_CA>,
666 <&cru CLK_VDEC_HEVC_CA>,
667 <&cru ACLK_JPEG>,
668 <&cru HCLK_JPEG>;
674 clocks = <&cru HCLK_EMMC>,
675 <&cru CLK_EMMC>,
676 <&cru HCLK_NANDC>,
677 <&cru CLK_NANDC>,
678 <&cru HCLK_SFC>,
679 <&cru HCLK_SFCXIP>,
680 <&cru SCLK_SFC>;
687 clocks = <&cru HCLK_SDIO>,
688 <&cru CLK_SDIO>;
693 clocks = <&cru HCLK_USBHOST>,
694 <&cru HCLK_USBHOST_ARB>,
695 <&cru CLK_USBHOST_UTMI_OHCI>,
696 <&cru ACLK_USBOTG>,
697 <&cru CLK_USBOTG_REF>;
743 clocks = <&cru ACLK_DMAC>;
891 cru: clock-controller@ff490000 { label
892 compatible = "rockchip,rv1126-cru";
900 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
901 <&cru PLL_HPLL>, <&cru ARMCLK>,
902 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
903 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
904 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
905 <&cru HCLK_PDCORE_NIU>;
921 clocks = <&cru PCLK_CSIPHY0>;
930 clocks = <&cru PCLK_CSIPHY1>;
940 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
942 resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>;
963 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
965 assigned-clocks = <&cru USB480M>;
967 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
987 clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
991 resets = <&cru SRST_DSIPHY_P>;
1002 clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>;
1018 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1031 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1044 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1057 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1070 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1081 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1092 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1103 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1131 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1146 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1161 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1176 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1189 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1204 clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>;
1228 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1230 resets = <&cru SRST_SARADC_P>;
1240 assigned-clocks = <&cru CLK_CPU_TSADC>;
1242 clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>,
1243 <&cru CLK_CPU_TSADCPHY>;
1245 resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>,
1246 <&cru SRST_CPU_TSADCPHY>;
1258 assigned-clocks = <&cru CLK_NPU_TSADC>;
1260 clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>,
1261 <&cru CLK_NPU_TSADCPHY>;
1263 resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>,
1264 <&cru SRST_NPU_TSADCPHY>;
1275 assigned-clocks = <&cru CLK_CAN>;
1277 clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>;
1279 resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>;
1288 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
1295 clocks = <&cru PCLK_WDT>;
1297 resets = <&cru SRST_WDT_P>;
1307 clocks = <&cru PCLK_MAILBOX>;
1317 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
1319 resets = <&cru SRST_DECOM_D>;
1329 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
1333 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
1335 rockchip,cru = <&cru>;
1354 clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>;
1370 clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>;
1385 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1402 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
1423 clocks = <&cru SCLK_DDRCLK>;
1477 clocks = <&cru ACLK_CIF>, <&cru ACLK_CIFLITE>,
1478 <&cru HCLK_CIF>, <&cru HCLK_CIFLITE>,
1479 <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>;
1483 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
1484 <&cru SRST_CIF_D>, <&cru SRST_CIF_P>,
1485 <&cru SRST_CIF_I>, <&cru SRST_CIF_RX_P>,
1486 <&cru SRST_CIFLITE_A>, <&cru SRST_CIFLITE_H>,
1487 <&cru SRST_CIFLITE_D>, <&cru SRST_CIFLITE_RX_P>;
1493 assigned-clocks = <&cru DCLK_CIF>, <&cru DCLK_CIFLITE>;
1505 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
1516 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
1529 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1556 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1571 clocks = <&cru PCLK_CSIHOST>, <&cru SRST_CSIHOST_P>;
1581 clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>;
1583 resets = <&cru SRST_DSIHOST_P>;
1609 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1610 <&cru CLK_ISP>;
1612 assigned-clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1625 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1639 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
1640 <&cru CLK_ISPP>;
1642 assigned-clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
1643 <&cru CLK_ISPP>;
1658 clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>;
1671 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>,
1672 <&cru CLK_VDEC_CA>, <&cru CLK_VDEC_CORE>,
1673 <&cru CLK_VDEC_HEVC_CA>;
1676 resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>,
1677 <&cru SRST_VDEC_CA>, <&cru SRST_VDEC_CORE>,
1678 <&cru SRST_VDEC_HEVC_CA>;
1694 clocks = <&cru ACLK_VDEC>, <&cru HCLK_VDEC>;
1705 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
1707 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>;
1722 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
1724 resets = <&cru SRST_JPEG_A>, <&cru SRST_JPEG_H>;
1740 clocks = <&cru ACLK_JPEG>, <&cru HCLK_JPEG>;
1751 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>,
1752 <&cru CLK_VENC_CORE>;
1754 resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>,
1755 <&cru SRST_VENC_CORE>;
1757 assigned-clocks = <&cru ACLK_VENC>, <&cru CLK_VENC_CORE>;
1797 clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>;
1813 clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>;
1815 resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>;
1827 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
1828 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
1829 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
1830 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
1835 resets = <&cru SRST_GMAC_A>;
1873 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
1874 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1889 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
1890 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1904 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
1905 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1920 clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>;
1932 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1936 assigned-clocks = <&cru SCLK_SFC>;
1945 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>, <&cru PCLK_PDNPU>, <&cru CLK_CORE_NPU>;
1947 assigned-clocks = <&cru CLK_CORE_NPU>;
1993 clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>,
1994 <&cru HCLK_PDUSB>;
2008 resets = <&cru SRST_USBOTG_A>;
2024 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
2037 clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
2071 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2084 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2097 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2110 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;