Lines Matching +full:0 +full:xffb80000
46 #size-cells = <0>;
51 reg = <0xf00>;
61 reg = <0xf01>;
71 reg = <0xf02>;
81 reg = <0xf03>;
94 arm,psci-suspend-param = <0x0010000>;
164 bus-id = <0>;
165 cfg-val = <0x00300020>;
166 enable-msk = <0x7144>;
171 cfg-val = <0x00300020>;
172 enable-msk = <0x70ff>;
177 cfg-val = <0x00300020>;
178 enable-msk = <0x70ff>;
183 cfg-val = <0x00300020>;
184 enable-msk = <0x70ff>;
189 cfg-val = <0x00300020>;
190 enable-msk = <0x7011>;
195 cfg-val = <0x00300020>;
196 enable-msk = <0x7011>;
201 cfg-val = <0x00300020>;
202 enable-msk = <0x7011>;
207 cfg-val = <0x00300020>;
208 enable-msk = <0x0>;
213 cfg-val = <0x00300020>;
214 enable-msk = <0x0>;
219 cfg-val = <0x00300020>;
220 enable-msk = <0x0>;
225 cfg-val = <0x00300020>;
226 enable-msk = <0x0>;
231 cfg-val = <0x00300020>;
232 enable-msk = <0x7000>;
266 rockchip,wake-irq = <0>;
267 rockchip,irq-mode-enable = <0>;
301 size = <0x6800000>;
306 reg = <0x8000000 0x100000>;
307 record-size = <0x20000>;
308 console-size = <0x40000>;
309 ftrace-size = <0x00000>;
310 pmsg-size = <0x40000>;
318 rockchip,sleep-debug-en = <0>;
320 (0
328 (0
344 thermal-sensors = <&cpu_tsadc 0>;
352 thermal-sensors = <&npu_tsadc 0>;
369 #clock-cells = <0>;
376 #clock-cells = <0>;
383 #clock-cells = <0>;
388 reg = <0xfe000000 0x20000>;
396 #size-cells = <0>;
398 port@0 {
399 reg = <0>;
401 #size-cells = <0>;
403 rgb_in_vop: endpoint@0 {
404 reg = <0>;
415 reg = <0xfe020000 0x1000>;
423 offset = <0x200>;
436 reg = <0xfe810000 0x20>;
441 reg = <0xfe810080 0x20>;
446 reg = <0xfe850000 0x20>;
451 reg = <0xfe860000 0x20>;
456 reg = <0xfe860080 0x20>;
461 reg = <0xfe860200 0x20>;
466 reg = <0xfe86c000 0x20>;
471 reg = <0xfe870000 0x20>;
476 reg = <0xfe870080 0x20>;
481 reg = <0xfe870100 0x20>;
486 reg = <0xfe880000 0x20>;
491 reg = <0xfe880080 0x20>;
496 reg = <0xfe890000 0x20>;
501 reg = <0xfe890080 0x20>;
506 reg = <0xfe890100 0x20>;
511 reg = <0xfe8a0000 0x20>;
516 reg = <0xfe8a0080 0x20>;
521 reg = <0xfe8a0100 0x20>;
526 reg = <0xfe8a0180 0x20>;
531 reg = <0xfe8b0000 0x20>;
536 reg = <0xfe8c0000 0x20>;
541 reg = <0xfe8d0000 0x20>;
548 #address-cells = <0>;
550 reg = <0xfeff1000 0x1000>,
551 <0xfeff2000 0x2000>,
552 <0xfeff4000 0x2000>,
553 <0xfeff6000 0x2000>;
559 reg = <0xff010000 0x1000>,
560 <0xff012000 0x1000>,
561 <0xff014000 0x1000>,
562 <0xff016000 0x1000>;
567 reg = <0xff040000 0x100>;
569 #size-cells = <0>;
571 pvtm@0 {
572 reg = <0>;
582 reg = <0xff3e0000 0x1000>;
588 #size-cells = <0>;
706 reg = <0xff3f0000 0x1000>;
709 #size-cells = <0>;
713 pinctrl-0 = <&i2c0_xfer>;
719 reg = <0xff400000 0x1000>;
722 #size-cells = <0>;
727 pinctrl-0 = <&i2c2_xfer>;
739 reg = <0xff4e0000 0x4000>;
750 reg = <0xff410000 0x100>;
759 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
765 reg = <0xff430000 0x10>;
768 pinctrl-0 = <&pwm0m0_pins>;
776 reg = <0xff430010 0x10>;
779 pinctrl-0 = <&pwm1m0_pins>;
787 reg = <0xff430020 0x10>;
790 pinctrl-0 = <&pwm2m0_pins>;
798 reg = <0xff430030 0x10>;
801 pinctrl-0 = <&pwm3m0_pins>;
809 reg = <0xff440000 0x10>;
812 pinctrl-0 = <&pwm4m0_pins>;
820 reg = <0xff440010 0x10>;
823 pinctrl-0 = <&pwm5m0_pins>;
831 reg = <0xff440020 0x10>;
834 pinctrl-0 = <&pwm6m0_pins>;
842 reg = <0xff440030 0x10>;
845 pinctrl-0 = <&pwm7m0_pins>;
853 reg = <0xff450000 0x1000>;
856 #size-cells = <0>;
859 dmas = <&dmac 1>, <&dmac 0>;
862 pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>;
869 reg = <0xff470000 0x100>;
871 #size-cells = <0>;
885 reg = <0xff480000 0x1000>;
893 reg = <0xff490000 0x1000>;
920 reg = <0xff4b0000 0x8000>;
929 reg = <0xff4b8000 0x8000>;
938 reg = <0xff4c0000 0x8000>;
944 #clock-cells = <0>;
948 #phy-cells = <0>;
961 reg = <0xff4c8000 0x8000>;
969 #clock-cells = <0>;
974 #phy-cells = <0>;
984 reg = <0xff4d0000 0x500>;
990 #clock-cells = <0>;
993 #phy-cells = <0>;
1000 reg = <0xff500000 0x10000>;
1008 reg = <0xff500000 0x2000>;
1014 reg = <0xff510000 0x1000>;
1017 #size-cells = <0>;
1021 pinctrl-0 = <&i2c1_xfer>;
1027 reg = <0xff520000 0x1000>;
1030 #size-cells = <0>;
1034 pinctrl-0 = <&i2c3m0_xfer>;
1040 reg = <0xff530000 0x1000>;
1043 #size-cells = <0>;
1047 pinctrl-0 = <&i2c4m0_xfer>;
1053 reg = <0xff540000 0x1000>;
1056 #size-cells = <0>;
1060 pinctrl-0 = <&i2c5m0_xfer>;
1066 reg = <0xff550000 0x10>;
1069 pinctrl-0 = <&pwm8m0_pins>;
1077 reg = <0xff550010 0x10>;
1080 pinctrl-0 = <&pwm9m0_pins>;
1088 reg = <0xff550020 0x10>;
1091 pinctrl-0 = <&pwm10m0_pins>;
1099 reg = <0xff550030 0x10>;
1102 pinctrl-0 = <&pwm11m0_pins>;
1110 reg = <0xff560000 0x100>;
1119 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
1125 reg = <0xff570000 0x100>;
1134 pinctrl-0 = <&uart2m1_xfer>;
1140 reg = <0xff580000 0x100>;
1149 pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>;
1155 reg = <0xff590000 0x100>;
1164 pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
1170 reg = <0xff5a0000 0x100>;
1179 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
1185 reg = <0xff5b0000 0x1000>;
1188 #size-cells = <0>;
1194 pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>;
1201 reg = <0xff5c0000 0x1000>;
1210 reg = <0x07 0x10>;
1213 reg = <0x17 0x1>;
1216 reg = <0x18 0x1>;
1219 reg = <0x19 0x1>;
1225 reg = <0xff5e0000 0x100>;
1237 reg = <0xff5f0000 0x100>;
1255 reg = <0xff5f8000 0x100>;
1273 reg = <0xff610000 0x100>;
1286 reg = <0xff660000 0x20>;
1294 reg = <0xff680000 0x100>;
1305 reg = <0xff6a0000 0x1000>;
1315 reg = <0xff6c0000 0x1000>;
1321 data-cached = <0>;
1327 reg = <0xff800000 0x1000>;
1338 pinctrl-0 = <&i2s0m0_sclk_tx
1352 reg = <0xff810000 0x1000>;
1359 pinctrl-0 = <&i2s1m0_sclk
1368 reg = <0xff820000 0x1000>;
1375 pinctrl-0 = <&i2s2m0_sclk
1384 reg = <0xff830000 0x1000>;
1390 pinctrl-0 = <&pdmm0_clk
1401 reg = <0xff840000 0x1000>;
1407 pinctrl-0 = <&audpwmm0_pins>;
1414 reg = <0xff9c0000 0x400>;
1440 auto-freq-en = <0>;
1473 reg = <0xffae0000 0x10000>;
1502 reg = <0xffae0800 0x100>;
1508 #iommu-cells = <0>;
1514 reg = <0xffaf0000 0x1000>;
1525 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
1537 #size-cells = <0>;
1539 vop_out_rgb: endpoint@0 {
1540 reg = <0>;
1553 reg = <0xffb00f00 0x100>;
1558 #iommu-cells = <0>;
1566 reg = <0xffb10000 0x10000>;
1579 reg = <0xffb30000 0x500>;
1589 #size-cells = <0>;
1604 reg = <0xffb50000 0x10000>;
1622 reg = <0xffb51a00 0x100>;
1628 #iommu-cells = <0>;
1635 reg = <0xffb60000 0x20000>;
1653 reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>;
1661 #iommu-cells = <0>;
1668 reg = <0xffb80000 0x400>;
1684 rockchip,taskqueue-node = <0>;
1685 rockchip,resetgroup-node = <0>;
1691 reg = <0xffb80480 0x40>, <0xffb804c0 0x40>;
1697 #iommu-cells = <0>;
1703 reg = <0xffb90000 0x400>;
1719 reg = <0xffb90400 0x400>;
1736 reg = <0xffb90800 0x40>;
1742 #iommu-cells = <0>;
1748 reg = <0xffbb0000 0x400>;
1793 reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>;
1800 #iommu-cells = <0>;
1807 reg = <0xffc00000 0x100>;
1809 #size-cells = <0>;
1822 reg = <0xffc40000 0x0ffff>;
1848 #address-cells = <0x1>;
1849 #size-cells = <0x0>;
1855 snps,blen = <0 0 0 0 16 8 4>;
1871 reg = <0xffc50000 0x4000>;
1876 fifo-depth = <0x100>;
1879 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1887 reg = <0xffc60000 0x4000>;
1893 fifo-depth = <0x100>;
1896 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1902 reg = <0xffc70000 0x4000>;
1907 fifo-depth = <0x100>;
1910 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
1917 reg = <0xffc80000 0x4000>;
1919 nandc_id = <0>;
1923 pinctrl-0 = <&flash_pins>;
1930 reg = <0xffc90000 0x4000>;
1935 pinctrl-0 = <&flash_pins>;
1944 reg = <0xffbc0000 0x4000>;
2000 reg = <0xffd00000 0x100000>;
2022 reg = <0xffe00000 0x10000>;
2035 reg = <0xffe10000 0x10000>;
2056 reg = <0xff460000 0x100>;
2069 reg = <0xff620000 0x100>;
2082 reg = <0xff630000 0x100>;
2095 reg = <0xff640000 0x100>;
2108 reg = <0xff650000 0x100>;