Lines Matching +full:rk3588 +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3588-power.h>
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "rockchip,rk3588";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu-map {
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 capacity-dmips-mhz = <530>;
101 compatible = "arm,cortex-a55";
103 enable-method = "psci";
104 capacity-dmips-mhz = <530>;
109 compatible = "arm,cortex-a55";
111 enable-method = "psci";
112 capacity-dmips-mhz = <530>;
117 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 capacity-dmips-mhz = <530>;
125 compatible = "arm,cortex-a76";
127 enable-method = "psci";
128 capacity-dmips-mhz = <1024>;
133 compatible = "arm,cortex-a76";
135 enable-method = "psci";
136 capacity-dmips-mhz = <1024>;
141 compatible = "arm,cortex-a76";
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
149 compatible = "arm,cortex-a76";
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
156 arm_pmu: arm-pmu {
157 compatible = "arm,armv8-pmuv3";
159 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
165 compatible = "linaro,optee-tz";
170 compatible = "arm,scmi-smc";
172 arm,smc-id = <0x82000010>;
173 #address-cells = <1>;
174 #size-cells = <0>;
178 #clock-cells = <1>;
180 assigned-clocks = <&scmi_clk SCMI_SPLL>;
181 assigned-clock-rates = <700000000>;
186 #reset-cells = <1>;
191 compatible = "arm,sdei-1.0";
197 compatible = "arm,psci-1.0";
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <702000000>;
205 clock-output-names = "spll";
209 compatible = "arm,armv8-timer";
217 compatible = "fixed-clock";
218 #clock-cells = <0>;
219 clock-frequency = <32768>;
220 clock-output-names = "xin32k";
224 compatible = "fixed-clock";
225 #clock-cells = <0>;
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
231 compatible = "mmio-sram";
233 #address-cells = <1>;
234 #size-cells = <1>;
238 compatible = "arm,scmi-shmem";
244 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
245 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
246 <&cru ACLK_USB3OTG0>;
247 clock-names = "ref", "suspend", "bus";
248 #address-cells = <2>;
249 #size-cells = <2>;
257 power-domains = <&power RK3588_PD_USB>;
258 resets = <&cru SRST_A_USB3OTG0>;
259 reset-names = "usb3-otg";
262 phy-names = "usb2-phy";
265 snps,dis-u1-entry-quirk;
266 snps,dis-u2-entry-quirk;
267 snps,dis-u2-freeclk-exists-quirk;
268 snps,dis-del-phy-power-chg-quirk;
269 snps,dis-tx-ipgap-linecheck-quirk;
275 compatible = "generic-ehci";
278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
279 clock-names = "usbhost", "arbiter";
281 phy-names = "usb2-phy";
282 power-domains = <&power RK3588_PD_USB>;
287 compatible = "generic-ohci";
290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
291 clock-names = "usbhost", "arbiter";
293 phy-names = "usb2-phy";
294 power-domains = <&power RK3588_PD_USB>;
299 compatible = "generic-ehci";
302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
303 clock-names = "usbhost", "arbiter";
305 phy-names = "usb2-phy";
306 power-domains = <&power RK3588_PD_USB>;
311 compatible = "generic-ohci";
314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
315 clock-names = "usbhost", "arbiter";
317 phy-names = "usb2-phy";
318 power-domains = <&power RK3588_PD_USB>;
323 compatible = "arm,smmu-v3";
329 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
330 #iommu-cells = <1>;
335 compatible = "arm,smmu-v3";
341 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
342 #iommu-cells = <1>;
347 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
348 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
349 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>;
350 clock-names = "ref", "suspend", "bus", "utmi";
351 #address-cells = <2>;
352 #size-cells = <2>;
360 power-domains = <&power RK3588_PD_PHP>;
361 resets = <&cru SRST_A_USB3OTG2>;
362 reset-names = "usb3-host";
366 snps,dis-u2-freeclk-exists-quirk;
367 snps,dis-del-phy-power-chg-quirk;
368 snps,dis-tx-ipgap-linecheck-quirk;
374 compatible = "rockchip,rk3588-sys-grf", "syscon";
379 compatible = "rockchip,rk3588-vo-grf", "syscon";
384 compatible = "rockchip,rk3588-vo-grf", "syscon";
389 compatible = "rockchip,rk3588-usb-grf", "syscon";
394 compatible = "rockchip,rk3588-php-grf", "syscon";
399 compatible = "rockchip,pipe-phy-grf", "syscon";
404 compatible = "rockchip,pipe-phy-grf", "syscon";
409 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
414 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
415 "simple-mfd";
417 #address-cells = <1>;
418 #size-cells = <1>;
420 u2phy0: usb2-phy@0 {
421 compatible = "rockchip,rk3588-usb2phy";
424 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
425 reset-names = "phy", "apb";
426 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
427 clock-names = "phyclk";
428 #clock-cells = <0>;
431 u2phy0_otg: otg-port {
432 #phy-cells = <0>;
439 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
440 "simple-mfd";
442 #address-cells = <1>;
443 #size-cells = <1>;
445 u2phy2: usb2-phy@8000 {
446 compatible = "rockchip,rk3588-usb2phy";
449 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
450 reset-names = "phy", "apb";
451 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
452 clock-names = "phyclk";
453 #clock-cells = <0>;
456 u2phy2_host: host-port {
457 #phy-cells = <0>;
464 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
465 "simple-mfd";
467 #address-cells = <1>;
468 #size-cells = <1>;
470 u2phy3: usb2-phy@c000 {
471 compatible = "rockchip,rk3588-usb2phy";
474 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
475 reset-names = "phy", "apb";
476 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
477 clock-names = "phyclk";
478 #clock-cells = <0>;
481 u2phy3_host: host-port {
482 #phy-cells = <0>;
489 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
494 compatible = "rockchip,rk3588-ioc", "syscon";
499 compatible = "mmio-sram";
502 #address-cells = <1>;
503 #size-cells = <1>;
507 cru: clock-controller@fd7c0000 { label
508 compatible = "rockchip,rk3588-cru";
511 #clock-cells = <1>;
512 #reset-cells = <1>;
514 assigned-clocks =
515 <&cru PLL_PPLL>, <&cru PLL_CPLL>,
516 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
517 <&cru ARMCLK_L>, <&cru ARMCLK_B01>,
518 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>,
519 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
520 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
521 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
522 <&cru HCLK_PMU_CM0_ROOT>;
523 assigned-clock-rates =
535 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
537 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
538 clock-names = "i2c", "pclk";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c0m0_xfer>;
542 #address-cells = <1>;
543 #size-cells = <0>;
548 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
551 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
552 clock-names = "baudclk", "apb_pclk";
553 reg-shift = <2>;
554 reg-io-width = <4>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart0m0_xfer>;
562 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
564 #pwm-cells = <3>;
565 pinctrl-names = "active";
566 pinctrl-0 = <&pwm0m0_pins>;
567 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
568 clock-names = "pwm", "pclk";
573 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
575 #pwm-cells = <3>;
576 pinctrl-names = "active";
577 pinctrl-0 = <&pwm1m0_pins>;
578 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
579 clock-names = "pwm", "pclk";
584 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
586 #pwm-cells = <3>;
587 pinctrl-names = "active";
588 pinctrl-0 = <&pwm2m0_pins>;
589 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
590 clock-names = "pwm", "pclk";
595 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
599 #pwm-cells = <3>;
600 pinctrl-names = "active";
601 pinctrl-0 = <&pwm3m0_pins>;
602 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
603 clock-names = "pwm", "pclk";
607 pmu: power-management@fd8d8000 {
608 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
611 power: power-controller {
612 compatible = "rockchip,rk3588-power-controller";
613 #power-domain-cells = <1>;
614 #address-cells = <1>;
615 #size-cells = <0>;
619 power-domain@RK3588_PD_NPU {
621 #address-cells = <1>;
622 #size-cells = <0>;
624 power-domain@RK3588_PD_NPUTOP {
626 #address-cells = <1>;
627 #size-cells = <0>;
629 power-domain@RK3588_PD_NPU1 {
632 power-domain@RK3588_PD_NPU2 {
638 power-domain@RK3588_PD_GPU {
642 power-domain@RK3588_PD_VCODEC {
644 #address-cells = <1>;
645 #size-cells = <0>;
647 power-domain@RK3588_PD_RKVDEC0 {
650 power-domain@RK3588_PD_RKVDEC1 {
653 power-domain@RK3588_PD_VENC0 {
655 #address-cells = <1>;
656 #size-cells = <0>;
658 power-domain@RK3588_PD_VENC1 {
664 power-domain@RK3588_PD_VDPU {
666 #address-cells = <1>;
667 #size-cells = <0>;
669 power-domain@RK3588_PD_RGA30 {
672 power-domain@RK3588_PD_av1 {
676 power-domain@RK3588_PD_VOP {
679 power-domain@RK3588_PD_VO0 {
682 power-domain@RK3588_PD_VO1 {
685 power-domain@RK3588_PD_VI {
687 #address-cells = <1>;
688 #size-cells = <0>;
690 power-domain@RK3588_PD_ISP1 {
693 power-domain@RK3588_PD_FEC {
697 power-domain@RK3588_PD_RGA31 {
700 power-domain@RK3588_PD_USB {
703 power-domain@RK3588_PD_PHP {
705 #address-cells = <1>;
706 #size-cells = <0>;
708 power-domain@RK3588_PD_GMAC {
711 power-domain@RK3588_PD_PCIE {
715 power-domain@RK3588_PD_NVM {
717 #address-cells = <1>;
718 #size-cells = <0>;
720 power-domain@RK3588_PD_NVM0 {
724 power-domain@RK3588_PD_SDIO {
727 power-domain@RK3588_PD_AUDIO {
730 power-domain@RK3588_PD_SDMMC {
737 compatible = "rockchip,rk3588-bigcore0-pvtm";
739 #address-cells = <1>;
740 #size-cells = <0>;
743 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
744 clock-names = "clk", "pclk";
749 compatible = "rockchip,rk3588-bigcore1-pvtm";
751 #address-cells = <1>;
752 #size-cells = <0>;
755 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
756 clock-names = "clk", "pclk";
761 compatible = "rockchip,rk3588-litcore-pvtm";
763 #address-cells = <1>;
764 #size-cells = <0>;
767 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
768 clock-names = "clk", "pclk";
773 compatible = "rockchip,rk3588-npu-pvtm";
775 #address-cells = <1>;
776 #size-cells = <0>;
779 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
780 clock-names = "clk", "pclk";
781 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
782 reset-names = "rts", "rst-p";
787 compatible = "rockchip,rk3588-gpu-pvtm";
789 #address-cells = <1>;
790 #size-cells = <0>;
793 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
794 clock-names = "clk", "pclk";
795 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
796 reset-names = "rts", "rst-p";
801 compatible = "rockchip,iommu-v2";
804 interrupt-names = "npu0_mmu";
805 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
806 clock-names = "aclk", "iface";
807 power-domains = <&power RK3588_PD_NPUTOP>;
808 #iommu-cells = <0>;
813 compatible = "rockchip,iommu-v2";
816 interrupt-names = "npu1_mmu";
817 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
818 clock-names = "aclk", "iface";
819 power-domains = <&power RK3588_PD_NPU1>;
820 #iommu-cells = <0>;
825 compatible = "rockchip,iommu-v2";
828 interrupt-names = "npu2_mmu";
829 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
830 clock-names = "aclk", "iface";
831 power-domains = <&power RK3588_PD_NPU2>;
832 #iommu-cells = <0>;
837 compatible = "rockchip,iommu-v2";
840 interrupt-names = "irq_vdpu_mmu";
841 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
842 clock-names = "aclk", "iface";
843 power-domains = <&power RK3588_PD_VDPU>;
844 #iommu-cells = <0>;
849 compatible = "rockchip,iommu-v2";
852 interrupt-names = "rga3_0_mmu";
853 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
854 clock-names = "aclk", "iface";
855 power-domains = <&power RK3588_PD_RGA30>;
856 #iommu-cells = <0>;
861 compatible = "rockchip,iommu-v2";
864 interrupt-names = "rga3_1_mmu";
865 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
866 clock-names = "aclk", "iface";
867 power-domains = <&power RK3588_PD_RGA31>;
868 #iommu-cells = <0>;
873 compatible = "rockchip,iommu-v2";
876 interrupt-names = "irq_jpegd_mmu";
877 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
878 clock-names = "aclk", "iface";
879 power-domains = <&power RK3588_PD_VDPU>;
880 #iommu-cells = <0>;
885 compatible = "rockchip,iommu-v2";
888 interrupt-names = "irq_jpege0_mmu";
889 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
890 clock-names = "aclk", "iface";
891 power-domains = <&power RK3588_PD_VDPU>;
892 #iommu-cells = <0>;
897 compatible = "rockchip,iommu-v2";
900 interrupt-names = "irq_jpege1_mmu";
901 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
902 clock-names = "aclk", "iface";
903 power-domains = <&power RK3588_PD_VDPU>;
904 #iommu-cells = <0>;
909 compatible = "rockchip,iommu-v2";
912 interrupt-names = "irq_jpege2_mmu";
913 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
914 clock-names = "aclk", "iface";
915 power-domains = <&power RK3588_PD_VDPU>;
916 #iommu-cells = <0>;
921 compatible = "rockchip,iommu-v2";
924 interrupt-names = "irq_jpege3_mmu";
925 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
926 clock-names = "aclk", "iface";
927 power-domains = <&power RK3588_PD_VDPU>;
928 #iommu-cells = <0>;
933 compatible = "rockchip,iommu-v2";
936 interrupt-names = "irq_iep_mmu";
937 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
938 clock-names = "aclk", "iface";
939 #iommu-cells = <0>;
940 power-domains = <&power RK3588_PD_VDPU>;
945 compatible = "rockchip,iommu-v2";
949 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
950 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
951 clock-names = "aclk", "iface";
952 rockchip,disable-mmu-reset;
953 rockchip,enable-cmd-retry;
954 #iommu-cells = <0>;
955 power-domains = <&power RK3588_PD_VENC0>;
960 compatible = "rockchip,iommu-v2";
964 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
965 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
966 lock-names = "aclk", "iface";
967 rockchip,disable-mmu-reset;
968 rockchip,enable-cmd-retry;
969 #iommu-cells = <0>;
970 power-domains = <&power RK3588_PD_VENC1>;
975 compatible = "rockchip,iommu-v2";
978 interrupt-names = "irq_rkvdec0_mmu";
979 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
980 clock-names = "aclk", "iface";
981 rockchip,disable-mmu-reset;
982 rockchip,enable-cmd-retry;
983 #iommu-cells = <0>;
984 power-domains = <&power RK3588_PD_RKVDEC0>;
989 compatible = "rockchip,iommu-v2";
992 interrupt-names = "irq_rkvdec1_mmu";
993 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
994 clock-names = "aclk", "iface";
995 rockchip,disable-mmu-reset;
996 rockchip,enable-cmd-retry;
997 #iommu-cells = <0>;
998 power-domains = <&power RK3588_PD_RKVDEC1>;
1003 compatible = "rockchip,iommu-v2";
1006 interrupt-names = "isp0_mmu";
1007 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
1008 clock-names = "aclk", "iface";
1009 power-domains = <&power RK3588_PD_VI>;
1010 #iommu-cells = <0>;
1011 rockchip,disable-mmu-reset;
1016 compatible = "rockchip,iommu-v2";
1019 interrupt-names = "isp1_mmu";
1020 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
1021 clock-names = "aclk", "iface";
1022 power-domains = <&power RK3588_PD_ISP1>;
1023 #iommu-cells = <0>;
1024 rockchip,disable-mmu-reset;
1029 compatible = "rockchip,iommu-v2";
1032 interrupt-names = "fec0_mmu";
1033 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>;
1034 clock-names = "aclk", "iface";
1035 power-domains = <&power RK3588_PD_FEC>;
1036 #iommu-cells = <0>;
1041 compatible = "rockchip,iommu-v2";
1044 interrupt-names = "fec1_mmu";
1045 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>;
1046 clock-names = "aclk", "iface";
1047 power-domains = <&power RK3588_PD_FEC>;
1048 #iommu-cells = <0>;
1053 compatible = "rockchip,iommu-v2";
1056 interrupt-names = "vop_mmu";
1057 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1058 clock-names = "aclk", "iface";
1059 #iommu-cells = <0>;
1060 rockchip,disable-device-link-resume;
1064 spdif_tx2: spdif-tx@fddb0000 {
1065 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1069 dma-names = "tx";
1070 clock-names = "mclk", "hclk";
1071 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>;
1072 #sound-dai-cells = <0>;
1077 compatible = "rockchip,rk3588-i2s-tdm";
1080 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1081 clock-names = "mclk_tx", "hclk";
1083 dma-names = "tx";
1084 resets = <&cru SRST_M_I2S4_8CH_TX>;
1085 reset-names = "tx-m";
1086 #sound-dai-cells = <0>;
1090 spdif_tx3: spdif-tx@fdde0000 {
1091 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1095 dma-names = "tx";
1096 clock-names = "mclk", "hclk";
1097 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
1098 #sound-dai-cells = <0>;
1103 compatible = "rockchip,rk3588-i2s-tdm";
1106 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1107 clock-names = "mclk_tx", "hclk";
1109 dma-names = "tx";
1110 resets = <&cru SRST_M_I2S5_8CH_TX>;
1111 reset-names = "tx-m";
1112 #sound-dai-cells = <0>;
1117 compatible = "rockchip,rk3588-i2s-tdm";
1120 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1121 clock-names = "mclk_rx", "hclk";
1123 dma-names = "rx";
1124 resets = <&cru SRST_M_I2S9_8CH_RX>;
1125 reset-names = "rx-m";
1126 #sound-dai-cells = <0>;
1130 spdif_rx0: spdif-rx@fde08000 {
1131 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
1134 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
1135 clock-names = "mclk", "hclk";
1137 dma-names = "rx";
1138 resets = <&cru SRST_M_SPDIFRX0>;
1139 reset-names = "spdifrx-m";
1140 #sound-dai-cells = <0>;
1145 compatible = "rockchip,rk3588-edp";
1148 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
1149 <&cru CLK_EDP0_200M>;
1150 clock-names = "dp", "pclk", "spdif";
1151 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
1152 reset-names = "dp", "apb";
1154 phy-names = "dp";
1155 power-domains = <&power RK3588_PD_VO1>;
1161 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
1162 #address-cells = <3>;
1163 #size-cells = <2>;
1164 bus-range = <0x30 0x3f>;
1165 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1166 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1167 <&cru CLK_PCIE_AUX3>;
1168 clock-names = "aclk_mst", "aclk_slv",
1176 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1177 #interrupt-cells = <1>;
1178 interrupt-map-mask = <0 0 0 7>;
1179 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1183 linux,pci-domain = <3>;
1184 num-ib-windows = <8>;
1185 num-ob-windows = <8>;
1186 max-link-speed = <2>;
1187 msi-map = <0x3000 &its 0x3000 0x1000>;
1188 num-lanes = <1>;
1190 phy-names = "pcie-phy";
1191 power-domains = <&power RK3588_PD_PHP>;
1199 reg-names = "pcie-dbi", "pcie-apb";
1200 resets = <&cru SRST_PCIE3_POWER_UP>;
1201 reset-names = "pipe";
1204 pcie2x1l1_intc: legacy-interrupt-controller {
1205 interrupt-controller;
1206 #address-cells = <0>;
1207 #interrupt-cells = <1>;
1208 interrupt-parent = <&gic>;
1214 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
1215 #address-cells = <3>;
1216 #size-cells = <2>;
1217 bus-range = <0x40 0x4f>;
1218 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1219 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1220 <&cru CLK_PCIE_AUX4>;
1221 clock-names = "aclk_mst", "aclk_slv",
1229 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1230 #interrupt-cells = <1>;
1231 interrupt-map-mask = <0 0 0 7>;
1232 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1236 linux,pci-domain = <4>;
1237 num-ib-windows = <8>;
1238 num-ob-windows = <8>;
1239 max-link-speed = <2>;
1240 msi-map = <0x4000 &its 0x4000 0x1000>;
1241 num-lanes = <1>;
1243 phy-names = "pcie-phy";
1244 power-domains = <&power RK3588_PD_PHP>;
1251 reg-names = "pcie-dbi", "pcie-apb";
1252 resets = <&cru SRST_PCIE4_POWER_UP>;
1253 reset-names = "pipe";
1256 pcie2x1l2_intc: legacy-interrupt-controller {
1257 interrupt-controller;
1258 #address-cells = <0>;
1259 #interrupt-cells = <1>;
1260 interrupt-parent = <&gic>;
1266 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1270 interrupt-names = "macirq", "eth_wake_irq";
1273 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>,
1274 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>;
1275 clock-names = "stmmaceth", "aclk_mac",
1277 resets = <&cru SRST_A_GMAC1>;
1278 reset-names = "stmmaceth";
1280 snps,mixed-burst;
1283 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1285 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1289 compatible = "snps,dwmac-mdio";
1290 #address-cells = <0x1>;
1291 #size-cells = <0x0>;
1294 gmac1_stmmac_axi_setup: stmmac-axi-config {
1300 gmac1_mtl_rx_setup: rx-queues-config {
1301 snps,rx-queues-to-use = <2>;
1306 gmac1_mtl_tx_setup: tx-queues-config {
1307 snps,tx-queues-to-use = <2>;
1314 compatible = "snps,dwc-ahci";
1316 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1317 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>;
1318 clock-names = "sata", "pmalive", "rxoob", "ref";
1320 interrupt-names = "hostc";
1322 phy-names = "sata-phy";
1323 ports-implemented = <0x1>;
1324 power-domains = <&power RK3588_PD_PHP>;
1329 compatible = "snps,dwc-ahci";
1331 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1332 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>;
1333 clock-names = "sata", "pmalive", "rxoob", "ref";
1335 interrupt-names = "hostc";
1337 phy-names = "sata-phy";
1338 ports-implemented = <0x1>;
1339 power-domains = <&power RK3588_PD_PHP>;
1347 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1348 clock-names = "clk_sfc", "hclk_sfc";
1349 assigned-clocks = <&cru SCLK_SFC>;
1350 assigned-clock-rates = <100000000>;
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1357 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1362 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
1363 fifo-depth = <0x100>;
1364 max-frequency = <200000000>;
1365 pinctrl-names = "default";
1366 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1371 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1374 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1375 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1376 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1377 fifo-depth = <0x100>;
1378 max-frequency = <200000000>;
1383 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
1386 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>;
1387 assigned-clock-rates = <200000000>, <24000000>;
1388 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1389 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1390 <&cru TMCLK_EMMC>;
1391 clock-names = "core", "bus", "axi", "block", "timer";
1392 max-frequency = <200000000>;
1397 compatible = "rockchip,rk3588-i2s-tdm";
1400 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1401 clock-names = "mclk_tx", "mclk_rx", "hclk";
1403 dma-names = "tx", "rx";
1404 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1405 reset-names = "tx-m", "rx-m";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&i2s0_lrck
1417 #sound-dai-cells = <0>;
1422 compatible = "rockchip,rk3588-i2s-tdm";
1425 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1426 clock-names = "mclk_tx", "mclk_rx", "hclk";
1428 dma-names = "tx", "rx";
1429 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1430 reset-names = "tx-m", "rx-m";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&i2s1m0_lrck
1442 #sound-dai-cells = <0>;
1447 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1450 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1451 clock-names = "i2s_clk", "i2s_hclk";
1453 dma-names = "tx", "rx";
1454 pinctrl-names = "default";
1455 pinctrl-0 = <&i2s2m1_lrck
1459 #sound-dai-cells = <0>;
1464 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1467 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1468 clock-names = "i2s_clk", "i2s_hclk";
1470 dma-names = "tx", "rx";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&i2s3_lrck
1476 #sound-dai-cells = <0>;
1481 compatible = "rockchip,rk3588-pdm";
1483 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
1484 clock-names = "pdm_clk", "pdm_hclk";
1486 dma-names = "rx";
1487 pinctrl-names = "default";
1488 pinctrl-0 = <&pdm0m0_clk
1494 #sound-dai-cells = <0>;
1499 compatible = "rockchip,rk3588-pdm";
1501 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
1502 clock-names = "pdm_clk", "pdm_hclk";
1504 dma-names = "rx";
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&pdm1m0_clk
1512 #sound-dai-cells = <0>;
1517 compatible = "rockchip,rk3588-vad";
1519 reg-names = "vad";
1520 clocks = <&cru HCLK_VAD>;
1521 clock-names = "hclk";
1523 rockchip,audio-src = <0>;
1524 rockchip,det-channel = <0>;
1526 #sound-dai-cells = <0>;
1530 spdif_tx0: spdif-tx@fe4e0000 {
1531 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1535 dma-names = "tx";
1536 clock-names = "mclk", "hclk";
1537 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&spdif0m0_tx>;
1540 #sound-dai-cells = <0>;
1544 spdif_tx1: spdif-tx@fe4f0000 {
1545 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
1549 dma-names = "tx";
1550 clock-names = "mclk", "hclk";
1551 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&spdif1m0_tx>;
1554 #sound-dai-cells = <0>;
1558 acdcdig_dsm: codec-digital@fe500000 {
1559 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
1561 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
1562 clock-names = "dac", "pclk";
1563 resets = <&cru SRST_DAC_ACDCDIG>;
1564 reset-names = "reset" ;
1566 rockchip,pwm-output-mode;
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&auddsm_pins>;
1569 #sound-dai-cells = <0>;
1576 #hwlock-cells = <1>;
1579 gic: interrupt-controller@fe600000 {
1580 compatible = "arm,gic-v3";
1581 #interrupt-cells = <3>;
1582 #address-cells = <2>;
1583 #size-cells = <2>;
1585 interrupt-controller;
1590 its: interrupt-controller@fe640000 {
1591 compatible = "arm,gic-v3-its";
1592 msi-controller;
1593 #msi-cells = <1>;
1598 dmac0: dma-controller@fea10000 {
1603 clocks = <&cru ACLK_DMAC0>;
1604 clock-names = "apb_pclk";
1605 #dma-cells = <1>;
1606 arm,pl330-periph-burst;
1609 dmac1: dma-controller@fea30000 {
1614 clocks = <&cru ACLK_DMAC1>;
1615 clock-names = "apb_pclk";
1616 #dma-cells = <1>;
1617 arm,pl330-periph-burst;
1621 compatible = "rockchip,canfd-1.0";
1624 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
1625 clock-names = "baudclk", "apb_pclk";
1626 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
1627 reset-names = "can", "can-apb";
1628 pinctrl-names = "default";
1629 pinctrl-0 = <&can0m0_pins>;
1630 tx-fifo-depth = <1>;
1631 rx-fifo-depth = <6>;
1636 compatible = "rockchip,canfd-1.0";
1639 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
1640 clock-names = "baudclk", "apb_pclk";
1641 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
1642 reset-names = "can", "can-apb";
1643 pinctrl-names = "default";
1644 pinctrl-0 = <&can1m0_pins>;
1645 tx-fifo-depth = <1>;
1646 rx-fifo-depth = <6>;
1651 compatible = "rockchip,canfd-1.0";
1654 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
1655 clock-names = "baudclk", "apb_pclk";
1656 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
1657 reset-names = "can", "can-apb";
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&can2m0_pins>;
1660 tx-fifo-depth = <1>;
1661 rx-fifo-depth = <6>;
1666 compatible = "rockchip,hw-decompress";
1669 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
1670 clock-names = "aclk", "dclk", "pclk";
1671 resets = <&cru SRST_D_DECOM>;
1672 reset-names = "dresetn";
1677 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1679 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1680 clock-names = "i2c", "pclk";
1682 pinctrl-names = "default";
1683 pinctrl-0 = <&i2c1m0_xfer>;
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1690 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1692 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1693 clock-names = "i2c", "pclk";
1695 pinctrl-names = "default";
1696 pinctrl-0 = <&i2c2m0_xfer>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1703 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1705 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1706 clock-names = "i2c", "pclk";
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&i2c3m0_xfer>;
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1716 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1718 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1719 clock-names = "i2c", "pclk";
1721 pinctrl-names = "default";
1722 pinctrl-0 = <&i2c4m0_xfer>;
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1729 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1731 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1732 clock-names = "i2c", "pclk";
1734 pinctrl-names = "default";
1735 pinctrl-0 = <&i2c5m0_xfer>;
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1742 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1745 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1746 clock-names = "pclk", "timer";
1750 compatible = "snps,dw-wdt";
1752 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1753 clock-names = "tclk", "pclk";
1759 compatible = "rockchip,rk3066-spi";
1762 #address-cells = <1>;
1763 #size-cells = <0>;
1764 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1765 clock-names = "spiclk", "apb_pclk";
1767 dma-names = "tx", "rx";
1768 pinctrl-names = "default", "high_speed";
1769 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1770 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
1771 num-cs = <2>;
1776 compatible = "rockchip,rk3066-spi";
1779 #address-cells = <1>;
1780 #size-cells = <0>;
1781 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1782 clock-names = "spiclk", "apb_pclk";
1784 dma-names = "tx", "rx";
1785 pinctrl-names = "default", "high_speed";
1786 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1787 pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>;
1788 num-cs = <2>;
1793 compatible = "rockchip,rk3066-spi";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1799 clock-names = "spiclk", "apb_pclk";
1801 dma-names = "tx", "rx";
1802 pinctrl-names = "default", "high_speed";
1803 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1804 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
1805 num-cs = <2>;
1810 compatible = "rockchip,rk3066-spi";
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1815 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1816 clock-names = "spiclk", "apb_pclk";
1818 dma-names = "tx", "rx";
1819 pinctrl-names = "default", "high_speed";
1820 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1821 pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>;
1822 num-cs = <2>;
1827 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1830 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1831 clock-names = "baudclk", "apb_pclk";
1832 reg-shift = <2>;
1833 reg-io-width = <4>;
1835 pinctrl-names = "default";
1836 pinctrl-0 = <&uart1m0_xfer>;
1841 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1844 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1845 clock-names = "baudclk", "apb_pclk";
1846 reg-shift = <2>;
1847 reg-io-width = <4>;
1849 pinctrl-names = "default";
1850 pinctrl-0 = <&uart2m0_xfer>;
1855 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1858 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1859 clock-names = "baudclk", "apb_pclk";
1860 reg-shift = <2>;
1861 reg-io-width = <4>;
1863 pinctrl-names = "default";
1864 pinctrl-0 = <&uart3m0_xfer>;
1869 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1872 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1873 clock-names = "baudclk", "apb_pclk";
1874 reg-shift = <2>;
1875 reg-io-width = <4>;
1877 pinctrl-names = "default";
1878 pinctrl-0 = <&uart4m0_xfer>;
1883 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1886 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1887 clock-names = "baudclk", "apb_pclk";
1888 reg-shift = <2>;
1889 reg-io-width = <4>;
1891 pinctrl-names = "default";
1892 pinctrl-0 = <&uart5m0_xfer>;
1897 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1900 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1901 clock-names = "baudclk", "apb_pclk";
1902 reg-shift = <2>;
1903 reg-io-width = <4>;
1905 pinctrl-names = "default";
1906 pinctrl-0 = <&uart6m0_xfer>;
1911 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1914 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1915 clock-names = "baudclk", "apb_pclk";
1916 reg-shift = <2>;
1917 reg-io-width = <4>;
1919 pinctrl-names = "default";
1920 pinctrl-0 = <&uart7m0_xfer>;
1925 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1928 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1929 clock-names = "baudclk", "apb_pclk";
1930 reg-shift = <2>;
1931 reg-io-width = <4>;
1933 pinctrl-names = "default";
1934 pinctrl-0 = <&uart8m0_xfer>;
1939 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1942 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1943 clock-names = "baudclk", "apb_pclk";
1944 reg-shift = <2>;
1945 reg-io-width = <4>;
1947 pinctrl-names = "default";
1948 pinctrl-0 = <&uart9m0_xfer>;
1953 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1955 #pwm-cells = <3>;
1956 pinctrl-names = "active";
1957 pinctrl-0 = <&pwm4m0_pins>;
1958 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1959 clock-names = "pwm", "pclk";
1964 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1966 #pwm-cells = <3>;
1967 pinctrl-names = "active";
1968 pinctrl-0 = <&pwm5m0_pins>;
1969 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1970 clock-names = "pwm", "pclk";
1975 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1977 #pwm-cells = <3>;
1978 pinctrl-names = "active";
1979 pinctrl-0 = <&pwm6m0_pins>;
1980 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1981 clock-names = "pwm", "pclk";
1986 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1990 #pwm-cells = <3>;
1991 pinctrl-names = "active";
1992 pinctrl-0 = <&pwm7m0_pins>;
1993 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1994 clock-names = "pwm", "pclk";
1999 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2001 #pwm-cells = <3>;
2002 pinctrl-names = "active";
2003 pinctrl-0 = <&pwm8m0_pins>;
2004 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2005 clock-names = "pwm", "pclk";
2010 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2012 #pwm-cells = <3>;
2013 pinctrl-names = "active";
2014 pinctrl-0 = <&pwm9m0_pins>;
2015 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2016 clock-names = "pwm", "pclk";
2021 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2023 #pwm-cells = <3>;
2024 pinctrl-names = "active";
2025 pinctrl-0 = <&pwm10m0_pins>;
2026 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2027 clock-names = "pwm", "pclk";
2032 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2036 #pwm-cells = <3>;
2037 pinctrl-names = "active";
2038 pinctrl-0 = <&pwm11m0_pins>;
2039 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2040 clock-names = "pwm", "pclk";
2045 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2047 #pwm-cells = <3>;
2048 pinctrl-names = "active";
2049 pinctrl-0 = <&pwm12m0_pins>;
2050 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2051 clock-names = "pwm", "pclk";
2056 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2058 #pwm-cells = <3>;
2059 pinctrl-names = "active";
2060 pinctrl-0 = <&pwm13m0_pins>;
2061 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2062 clock-names = "pwm", "pclk";
2067 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2069 #pwm-cells = <3>;
2070 pinctrl-names = "active";
2071 pinctrl-0 = <&pwm14m0_pins>;
2072 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2073 clock-names = "pwm", "pclk";
2078 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2082 #pwm-cells = <3>;
2083 pinctrl-names = "active";
2084 pinctrl-0 = <&pwm15m0_pins>;
2085 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2086 clock-names = "pwm", "pclk";
2091 compatible = "rockchip,rk3588-tsadc";
2094 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2095 clock-names = "tsadc", "apb_pclk";
2096 assigned-clocks = <&cru CLK_TSADC>;
2097 assigned-clock-rates = <2000000>;
2098 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
2099 reset-names = "tsadc", "tsadc-apb";
2100 #thermal-sensor-cells = <1>;
2101 rockchip,hw-tshut-temp = <120000>;
2102 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
2103 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2104 pinctrl-names = "gpio", "otpout";
2105 pinctrl-0 = <&tsadc_gpio_func>;
2106 pinctrl-1 = <&tsadc_shut_org>;
2111 compatible = "rockchip,rk3588-saradc";
2114 #io-channel-cells = <1>;
2115 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2116 clock-names = "saradc", "apb_pclk";
2117 resets = <&cru SRST_P_SARADC>;
2118 reset-names = "saradc-apb";
2123 compatible = "rockchip,rk3588-mailbox",
2124 "rockchip,rk3368-mailbox";
2130 clocks = <&cru PCLK_MAILBOX0>;
2131 clock-names = "pclk_mailbox";
2132 #mbox-cells = <1>;
2137 compatible = "rockchip,rk3588-mailbox",
2138 "rockchip,rk3368-mailbox";
2144 clocks = <&cru PCLK_MAILBOX1>;
2145 clock-names = "pclk_mailbox";
2146 #mbox-cells = <1>;
2151 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2153 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2154 clock-names = "i2c", "pclk";
2156 pinctrl-names = "default";
2157 pinctrl-0 = <&i2c6m0_xfer>;
2158 #address-cells = <1>;
2159 #size-cells = <0>;
2164 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2166 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2167 clock-names = "i2c", "pclk";
2169 pinctrl-names = "default";
2170 pinctrl-0 = <&i2c7m0_xfer>;
2171 #address-cells = <1>;
2172 #size-cells = <0>;
2177 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2179 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2180 clock-names = "i2c", "pclk";
2182 pinctrl-names = "default";
2183 pinctrl-0 = <&i2c8m0_xfer>;
2184 #address-cells = <1>;
2185 #size-cells = <0>;
2190 compatible = "rockchip,rk3066-spi";
2193 #address-cells = <1>;
2194 #size-cells = <0>;
2195 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2196 clock-names = "spiclk", "apb_pclk";
2198 dma-names = "tx", "rx";
2199 pinctrl-names = "default", "high_speed";
2200 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2201 pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>;
2202 num-cs = <2>;
2207 compatible = "rockchip,rk3588-otp";
2209 #address-cells = <1>;
2210 #size-cells = <1>;
2211 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2212 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
2213 clock-names = "otpc", "apb", "arb", "phy";
2214 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2215 <&cru SRST_OTPC_ARB>;
2216 reset-names = "otpc", "apb", "arb";
2220 compatible = "rockchip,rk3588-mailbox",
2221 "rockchip,rk3368-mailbox";
2227 clocks = <&cru PCLK_MAILBOX2>;
2228 clock-names = "pclk_mailbox";
2229 #mbox-cells = <1>;
2233 dmac2: dma-controller@fed10000 {
2238 clocks = <&cru ACLK_DMAC2>;
2239 clock-names = "apb_pclk";
2240 #dma-cells = <1>;
2241 arm,pl330-periph-burst;
2245 compatible = "rockchip,rk3588-hdptx-phy";
2247 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2248 clock-names = "ref", "apb";
2249 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2250 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2251 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2252 <&cru SRST_HDPTX0_LCPLL>;
2253 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2256 #phy-cells = <0>;
2261 compatible = "rockchip,rk3588-usbdp-phy";
2263 rockchip,usb-grf = <&usb_grf>;
2264 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2265 rockchip,vo-grf = <&vo0_grf>;
2266 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
2267 <&cru CLK_USBDP_PHY0_IMMORTAL>,
2268 <&cru PCLK_USBDPPHY0>;
2269 clock-names = "refclk", "immortal", "pclk";
2270 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
2271 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
2272 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
2273 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
2274 <&cru SRST_P_USBDPPHY0>;
2275 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2278 usbdp_phy0_dp: dp-port {
2279 #phy-cells = <0>;
2283 usbdp_phy0_u3: u3-port {
2284 #phy-cells = <0>;
2290 compatible = "rockchip,rk3588-naneng-combphy";
2292 #phy-cells = <1>;
2293 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;
2294 clock-names = "refclk", "apbclk";
2295 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2296 assigned-clock-rates = <100000000>;
2297 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
2298 reset-names = "combphy-apb", "combphy";
2299 rockchip,pipe-grf = <&php_grf>;
2300 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2305 compatible = "rockchip,rk3588-naneng-combphy";
2307 #phy-cells = <1>;
2308 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>;
2309 clock-names = "refclk", "apbclk";
2310 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2311 assigned-clock-rates = <100000000>;
2312 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
2313 reset-names = "combphy-apb", "combphy";
2314 rockchip,pipe-grf = <&php_grf>;
2315 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2316 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
2321 compatible = "rockchip,rk3588-pinctrl";
2323 #address-cells = <2>;
2324 #size-cells = <2>;
2328 compatible = "rockchip,gpio-bank";
2331 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2333 gpio-controller;
2334 #gpio-cells = <2>;
2335 gpio-ranges = <&pinctrl 0 0 32>;
2336 interrupt-controller;
2337 #interrupt-cells = <2>;
2341 compatible = "rockchip,gpio-bank";
2344 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2346 gpio-controller;
2347 #gpio-cells = <2>;
2348 gpio-ranges = <&pinctrl 0 32 32>;
2349 interrupt-controller;
2350 #interrupt-cells = <2>;
2354 compatible = "rockchip,gpio-bank";
2357 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2359 gpio-controller;
2360 #gpio-cells = <2>;
2361 gpio-ranges = <&pinctrl 0 64 32>;
2362 interrupt-controller;
2363 #interrupt-cells = <2>;
2367 compatible = "rockchip,gpio-bank";
2370 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2372 gpio-controller;
2373 #gpio-cells = <2>;
2374 gpio-ranges = <&pinctrl 0 96 32>;
2375 interrupt-controller;
2376 #interrupt-cells = <2>;
2380 compatible = "rockchip,gpio-bank";
2383 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2385 gpio-controller;
2386 #gpio-cells = <2>;
2387 gpio-ranges = <&pinctrl 0 128 32>;
2388 interrupt-controller;
2389 #interrupt-cells = <2>;
2394 #include "rk3588s-pinctrl.dtsi"