Lines Matching full:cru
6 #include <dt-bindings/clock/rk3588-cru.h>
245 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
246 <&cru ACLK_USB3OTG0>;
258 resets = <&cru SRST_A_USB3OTG0>;
278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
348 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
349 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>;
361 resets = <&cru SRST_A_USB3OTG2>;
424 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
426 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
449 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
451 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
474 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
476 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
507 cru: clock-controller@fd7c0000 { label
508 compatible = "rockchip,rk3588-cru";
515 <&cru PLL_PPLL>, <&cru PLL_CPLL>,
516 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
517 <&cru ARMCLK_L>, <&cru ARMCLK_B01>,
518 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>,
519 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
520 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
521 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
522 <&cru HCLK_PMU_CM0_ROOT>;
537 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
551 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
567 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
578 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
589 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
602 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
743 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
755 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
767 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
779 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
781 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
793 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
795 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
805 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
817 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
829 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
841 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
853 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
865 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
877 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
889 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
901 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
913 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
925 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
937 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
950 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
965 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
979 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
993 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
1007 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
1020 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
1033 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>;
1045 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>;
1057 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1071 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>;
1080 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1084 resets = <&cru SRST_M_I2S4_8CH_TX>;
1097 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
1106 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1110 resets = <&cru SRST_M_I2S5_8CH_TX>;
1120 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1124 resets = <&cru SRST_M_I2S9_8CH_RX>;
1134 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
1138 resets = <&cru SRST_M_SPDIFRX0>;
1148 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
1149 <&cru CLK_EDP0_200M>;
1151 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
1165 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1166 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1167 <&cru CLK_PCIE_AUX3>;
1200 resets = <&cru SRST_PCIE3_POWER_UP>;
1218 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1219 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1220 <&cru CLK_PCIE_AUX4>;
1252 resets = <&cru SRST_PCIE4_POWER_UP>;
1273 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>,
1274 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>;
1277 resets = <&cru SRST_A_GMAC1>;
1316 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1317 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>;
1331 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1332 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>;
1347 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1349 assigned-clocks = <&cru SCLK_SFC>;
1361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1374 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1375 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1386 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>;
1388 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1389 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1390 <&cru TMCLK_EMMC>;
1400 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1404 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1425 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1429 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1450 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1467 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1483 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
1501 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
1520 clocks = <&cru HCLK_VAD>;
1537 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
1551 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
1561 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
1563 resets = <&cru SRST_DAC_ACDCDIG>;
1603 clocks = <&cru ACLK_DMAC0>;
1614 clocks = <&cru ACLK_DMAC1>;
1624 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
1626 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
1639 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
1641 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
1654 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
1656 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
1669 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
1671 resets = <&cru SRST_D_DECOM>;
1679 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1692 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1705 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1718 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1731 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1745 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1752 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1764 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1781 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1798 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1815 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1830 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1844 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1858 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1872 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1886 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1900 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1914 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1928 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1942 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1958 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1969 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1980 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1993 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2004 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2015 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2026 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2039 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2050 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2061 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2072 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2085 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2094 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2096 assigned-clocks = <&cru CLK_TSADC>;
2098 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
2102 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
2115 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2117 resets = <&cru SRST_P_SARADC>;
2130 clocks = <&cru PCLK_MAILBOX0>;
2144 clocks = <&cru PCLK_MAILBOX1>;
2153 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2166 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2179 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2195 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2211 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2212 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
2214 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2215 <&cru SRST_OTPC_ARB>;
2227 clocks = <&cru PCLK_MAILBOX2>;
2238 clocks = <&cru ACLK_DMAC2>;
2247 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2249 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2250 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2251 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2252 <&cru SRST_HDPTX0_LCPLL>;
2266 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
2267 <&cru CLK_USBDP_PHY0_IMMORTAL>,
2268 <&cru PCLK_USBDPPHY0>;
2270 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
2271 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
2272 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
2273 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
2274 <&cru SRST_P_USBDPPHY0>;
2293 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;
2295 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2297 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
2308 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>;
2310 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2312 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
2331 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2344 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2357 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2370 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2383 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;