Lines Matching +full:usbdpphy +full:- +full:grf
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy-snps-pcie3.h>
8 #include "rk3588-vccio3-pinctrl.dtsi"
20 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
23 clock-names = "ref", "suspend", "bus";
24 #address-cells = <2>;
25 #size-cells = <2>;
33 power-domains = <&power RK3588_PD_USB>;
35 reset-names = "usb3-otg";
38 phy-names = "usb2-phy";
41 snps,dis-u2-freeclk-exists-quirk;
42 snps,dis-del-phy-power-chg-quirk;
43 snps,dis-tx-ipgap-linecheck-quirk;
49 compatible = "rockchip,pcie30-phy-grf", "syscon";
54 compatible = "rockchip,pipe-phy-grf", "syscon";
59 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
64 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
65 "simple-mfd";
67 #address-cells = <1>;
68 #size-cells = <1>;
70 u2phy1: usb2-phy@4000 {
71 compatible = "rockchip,rk3588-usb2phy";
75 reset-names = "phy", "apb";
77 clock-names = "phyclk";
78 #clock-cells = <0>;
81 u2phy1_otg: otg-port {
82 #phy-cells = <0>;
89 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
93 spdif_tx5: spdif-tx@fddb8000 {
94 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
98 dma-names = "tx";
99 clock-names = "mclk", "hclk";
101 #sound-dai-cells = <0>;
106 compatible = "rockchip,rk3588-i2s-tdm";
110 clock-names = "mclk_tx", "hclk";
112 dma-names = "tx";
114 reset-names = "tx-m";
115 #sound-dai-cells = <0>;
119 spdif_tx4: spdif-tx@fdde8000 {
120 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
124 dma-names = "tx";
125 clock-names = "mclk", "hclk";
127 #sound-dai-cells = <0>;
132 compatible = "rockchip,rk3588-i2s-tdm";
136 clock-names = "mclk_tx", "hclk";
138 dma-names = "tx";
140 reset-names = "tx-m";
141 #sound-dai-cells = <0>;
146 compatible = "rockchip,rk3588-i2s-tdm";
150 clock-names = "mclk_rx", "hclk";
152 dma-names = "rx";
154 reset-names = "rx-m";
155 #sound-dai-cells = <0>;
160 compatible = "rockchip,rk3588-i2s-tdm";
164 clock-names = "mclk_rx", "hclk";
166 dma-names = "rx";
168 reset-names = "rx-m";
169 #sound-dai-cells = <0>;
173 spdif_rx1: spdif-rx@fde10000 {
174 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
178 clock-names = "mclk", "hclk";
180 dma-names = "rx";
182 reset-names = "spdifrx-m";
183 #sound-dai-cells = <0>;
187 spdif_rx2: spdif-rx@fde18000 {
188 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
192 clock-names = "mclk", "hclk";
194 dma-names = "rx";
196 reset-names = "spdifrx-m";
197 #sound-dai-cells = <0>;
202 compatible = "rockchip,rk3588-edp";
207 clock-names = "dp", "pclk", "spdif";
209 reset-names = "dp", "apb";
211 phy-names = "dp";
212 power-domains = <&power RK3588_PD_VO1>;
213 rockchip,grf = <&vo1_grf>;
218 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
219 #address-cells = <3>;
220 #size-cells = <2>;
221 bus-range = <0x00 0x0f>;
225 clock-names = "aclk_mst", "aclk_slv",
233 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
234 #interrupt-cells = <1>;
235 interrupt-map-mask = <0 0 0 7>;
236 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
240 linux,pci-domain = <0>;
241 num-ib-windows = <16>;
242 num-ob-windows = <16>;
243 max-link-speed = <3>;
244 msi-map = <0x0000 &its 0x0000 0x1000>;
245 num-lanes = <4>;
247 phy-names = "pcie-phy";
248 power-domains = <&power RK3588_PD_PCIE>;
255 reg-names = "pcie-dbi", "pcie-apb";
257 reset-names = "pipe";
260 pcie3x4_intc: legacy-interrupt-controller {
261 interrupt-controller;
262 #address-cells = <0>;
263 #interrupt-cells = <1>;
264 interrupt-parent = <&gic>;
270 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
271 #address-cells = <3>;
272 #size-cells = <2>;
273 bus-range = <0x10 0x1f>;
277 clock-names = "aclk_mst", "aclk_slv",
285 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
286 #interrupt-cells = <1>;
287 interrupt-map-mask = <0 0 0 7>;
288 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
292 linux,pci-domain = <1>;
293 num-ib-windows = <16>;
294 num-ob-windows = <16>;
295 max-link-speed = <3>;
296 msi-map = <0x1000 &its 0x1000 0x1000>;
297 num-lanes = <2>;
299 phy-names = "pcie-phy";
300 power-domains = <&power RK3588_PD_PHP>;
307 reg-names = "pcie-dbi", "pcie-apb";
309 reset-names = "pipe";
312 pcie3x2_intc: legacy-interrupt-controller {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <1>;
316 interrupt-parent = <&gic>;
322 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
323 #address-cells = <3>;
324 #size-cells = <2>;
325 bus-range = <0x20 0x2f>;
329 clock-names = "aclk_mst", "aclk_slv",
337 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
338 #interrupt-cells = <1>;
339 interrupt-map-mask = <0 0 0 7>;
340 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
344 linux,pci-domain = <2>;
345 num-ib-windows = <8>;
346 num-ob-windows = <8>;
347 max-link-speed = <2>;
348 msi-map = <0x2000 &its 0x2000 0x1000>;
349 num-lanes = <1>;
351 phy-names = "pcie-phy";
352 power-domains = <&power RK3588_PD_PHP>;
359 reg-names = "pcie-dbi", "pcie-apb";
361 reset-names = "pipe";
364 pcie2x1l0_intc: legacy-interrupt-controller {
365 interrupt-controller;
366 #address-cells = <0>;
367 #interrupt-cells = <1>;
368 interrupt-parent = <&gic>;
374 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
378 interrupt-names = "macirq", "eth_wake_irq";
379 rockchip,grf = <&sys_grf>;
383 clock-names = "stmmaceth", "aclk_mac",
386 reset-names = "stmmaceth";
388 snps,mixed-burst;
391 snps,axi-config = <&gmac0_stmmac_axi_setup>;
392 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
393 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
397 compatible = "snps,dwmac-mdio";
398 #address-cells = <0x1>;
399 #size-cells = <0x0>;
402 gmac0_stmmac_axi_setup: stmmac-axi-config {
408 gmac0_mtl_rx_setup: rx-queues-config {
409 snps,rx-queues-to-use = <2>;
414 gmac0_mtl_tx_setup: tx-queues-config {
415 snps,tx-queues-to-use = <2>;
422 compatible = "snps,dwc-ahci";
426 clock-names = "sata", "pmalive", "rxoob", "ref";
428 interrupt-names = "hostc";
430 phy-names = "sata-phy";
431 ports-implemented = <0x1>;
432 power-domains = <&power RK3588_PD_PHP>;
437 compatible = "rockchip,rk3588-crypto";
440 clock-names = "sclk_crypto", "apkclk_crypto";
441 clock-frequency = <350000000>, <350000000>;
452 compatible = "rockchip,rk3588-hdptx-phy";
455 clock-names = "ref", "apb";
460 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
462 rockchip,grf = <&hdptxphy1_grf>;
463 #phy-cells = <0>;
468 compatible = "rockchip,rk3588-usbdp-phy";
470 rockchip,usb-grf = <&usb_grf>;
471 rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
472 rockchip,vo-grf = <&vo0_grf>;
476 clock-names = "refclk", "immortal", "pclk";
482 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
485 usbdp_phy1_dp: dp-port {
486 #phy-cells = <0>;
490 usbdp_phy1_u3: u3-port {
491 #phy-cells = <0>;
497 compatible = "rockchip,rk3588-naneng-combphy";
499 #phy-cells = <1>;
501 clock-names = "refclk", "apbclk";
502 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
503 assigned-clock-rates = <100000000>;
505 reset-names = "combphy-apb", "combphy";
506 rockchip,pipe-grf = <&php_grf>;
507 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
508 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
513 compatible = "rockchip,rk3588-pcie3-phy";
515 #phy-cells = <0>;
517 clock-names = "pclk";
519 reset-names = "phy";
520 rockchip,pipe-grf = <&php_grf>;
521 rockchip,phy-grf = <&pcie30_phy_grf>;