Lines Matching full:cru
21 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
22 <&cru ACLK_USB3OTG1>;
34 resets = <&cru SRST_A_USB3OTG1>;
74 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
76 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
100 clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>;
109 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
113 resets = <&cru SRST_M_I2S8_8CH_TX>;
126 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
135 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
139 resets = <&cru SRST_M_I2S6_8CH_TX>;
149 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
153 resets = <&cru SRST_M_I2S7_8CH_RX>;
163 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
167 resets = <&cru SRST_M_I2S10_8CH_RX>;
177 clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>;
181 resets = <&cru SRST_M_SPDIFRX1>;
191 clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>;
195 resets = <&cru SRST_M_SPDIFRX2>;
205 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>,
206 <&cru CLK_EDP1_200M>;
208 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
222 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
223 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
224 <&cru CLK_PCIE_AUX0>;
256 resets = <&cru SRST_PCIE0_POWER_UP>;
274 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
275 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
276 <&cru CLK_PCIE_AUX1>;
308 resets = <&cru SRST_PCIE1_POWER_UP>;
326 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
327 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
328 <&cru CLK_PCIE_AUX2>;
360 resets = <&cru SRST_PCIE2_POWER_UP>;
381 clocks = <&cru CLK_GMAC0>, <&cru ACLK_GMAC0>,
382 <&cru PCLK_GMAC0>, <&cru CLK_GMAC0_PTP_REF>;
385 resets = <&cru SRST_A_GMAC0>;
424 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
425 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>;
454 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
456 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
457 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
458 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
459 <&cru SRST_HDPTX1_LCPLL>;
473 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
474 <&cru CLK_USBDP_PHY1_IMMORTAL>,
475 <&cru PCLK_USBDPPHY1>;
477 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
478 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
479 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
480 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
481 <&cru SRST_P_USBDPPHY1>;
500 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>;
502 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
504 resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
516 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
518 resets = <&cru SRST_PCIE30_PHY>;