Lines Matching +full:0 +full:x40800000
31 reg = <0x0 0xfc400000 0x0 0x400000>;
50 reg = <0x0 0xfd5b8000 0x0 0x10000>;
55 reg = <0x0 0xfd5c0000 0x0 0x100>;
60 reg = <0x0 0xfd5cc000 0x0 0x4000>;
66 reg = <0x0 0xfd5d4000 0x0 0x4000>;
72 reg = <0x4000 0x10>;
78 #clock-cells = <0>;
82 #phy-cells = <0>;
90 reg = <0x0 0xfd5e4000 0x0 0x100>;
95 reg = <0x0 0xfddb8000 0x0 0x1000>;
101 #sound-dai-cells = <0>;
107 reg = <0x0 0xfddc8000 0x0 0x1000>;
115 #sound-dai-cells = <0>;
121 reg = <0x0 0xfdde8000 0x0 0x1000>;
127 #sound-dai-cells = <0>;
133 reg = <0x0 0xfddf4000 0x0 0x1000>;
141 #sound-dai-cells = <0>;
147 reg = <0x0 0xfddf8000 0x0 0x1000>;
155 #sound-dai-cells = <0>;
161 reg = <0x0 0xfde00000 0x0 0x1000>;
169 #sound-dai-cells = <0>;
175 reg = <0x0 0xfde10000 0x0 0x1000>;
183 #sound-dai-cells = <0>;
189 reg = <0x0 0xfde18000 0x0 0x1000>;
197 #sound-dai-cells = <0>;
203 reg = <0x0 0xfded0000 0x0 0x1000>;
221 bus-range = <0x00 0x0f>;
235 interrupt-map-mask = <0 0 0 7>;
236 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
237 <0 0 0 2 &pcie3x4_intc 1>,
238 <0 0 0 3 &pcie3x4_intc 2>,
239 <0 0 0 4 &pcie3x4_intc 3>;
240 linux,pci-domain = <0>;
244 msi-map = <0x0000 &its 0x0000 0x1000>;
249 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
250 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
251 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
252 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
253 reg = <0xa 0x40000000 0x0 0x400000>,
254 <0x0 0xfe150000 0x0 0x10000>;
262 #address-cells = <0>;
273 bus-range = <0x10 0x1f>;
287 interrupt-map-mask = <0 0 0 7>;
288 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
289 <0 0 0 2 &pcie3x2_intc 1>,
290 <0 0 0 3 &pcie3x2_intc 2>,
291 <0 0 0 4 &pcie3x2_intc 3>;
296 msi-map = <0x1000 &its 0x1000 0x1000>;
301 ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000
302 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
303 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
304 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
305 reg = <0xa 0x40400000 0x0 0x400000>,
306 <0x0 0xfe160000 0x0 0x10000>;
314 #address-cells = <0>;
325 bus-range = <0x20 0x2f>;
339 interrupt-map-mask = <0 0 0 7>;
340 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
341 <0 0 0 2 &pcie2x1l0_intc 1>,
342 <0 0 0 3 &pcie2x1l0_intc 2>,
343 <0 0 0 4 &pcie2x1l0_intc 3>;
348 msi-map = <0x2000 &its 0x2000 0x1000>;
353 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
354 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
355 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
356 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
357 reg = <0xa 0x40800000 0x0 0x400000>,
358 <0x0 0xfe170000 0x0 0x10000>;
366 #address-cells = <0>;
375 reg = <0x0 0xfe1b0000 0x0 0x10000>;
398 #address-cells = <0x1>;
399 #size-cells = <0x0>;
405 snps,blen = <0 0 0 0 16 8 4>;
423 reg = <0 0xfe220000 0 0x1000>;
431 ports-implemented = <0x1>;
438 reg = <0x0 0xfe370000 0x0 0x4000>;
447 reg = <0x0 0xfe378000 0x0 0x200>;
453 reg = <0x0 0xfed70000 0x0 0x2000>;
463 #phy-cells = <0>;
469 reg = <0x0 0xfed90000 0x0 0x10000>;
486 #phy-cells = <0>;
491 #phy-cells = <0>;
498 reg = <0x0 0xfee10000 0x0 0x100>;
508 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
514 reg = <0x0 0xfee80000 0x0 0x20000>;
515 #phy-cells = <0>;