Lines Matching refs:pmucru
533 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
546 pmucru: clock-controller@fdd00000 { label
547 compatible = "rockchip,rk3568-pmucru";
562 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,
563 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
580 <&pmucru CLK_RTC32K_FRAC>;
586 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
600 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
616 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
627 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
638 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
649 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
1433 <&pmucru PLL_HPLL>,
1469 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
2636 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
2638 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
2651 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
2653 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
2666 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
2668 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
2680 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
2696 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
2710 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
2726 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
2750 clocks = <&pmucru CLK_USBPHY0_REF>;
2774 clocks = <&pmucru CLK_USBPHY1_REF>;
2795 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
2816 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;