Lines Matching +full:1 +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 acodec_pins: acodec-pins {
18 <1 RK_PB1 5 &pcfg_pull_none>,
20 <1 RK_PA1 5 &pcfg_pull_none>,
22 <1 RK_PA0 5 &pcfg_pull_none>,
24 <1 RK_PA7 5 &pcfg_pull_none>,
26 <1 RK_PB0 5 &pcfg_pull_none>,
28 <1 RK_PA3 5 &pcfg_pull_none>,
30 <1 RK_PA5 5 &pcfg_pull_none>;
34 audiopwmout_pins: audiopwmout-pins {
37 <1 RK_PA0 4 &pcfg_pull_none>,
39 <1 RK_PA1 4 &pcfg_pull_none>;
43 audiopwmoutdiff_pins: audiopwmoutdiff-pins {
46 <1 RK_PA1 6 &pcfg_pull_none>,
48 <1 RK_PA0 6 &pcfg_pull_none>,
50 <1 RK_PA7 4 &pcfg_pull_none>,
52 <1 RK_PA6 4 &pcfg_pull_none>;
56 bt656m0_pins: bt656m0-pins {
59 <3 RK_PA0 2 &pcfg_pull_none>,
77 bt656m1_pins: bt656m1-pins {
82 <3 RK_PC6 5 &pcfg_pull_none>,
84 <3 RK_PC7 5 &pcfg_pull_none>,
86 <3 RK_PD0 5 &pcfg_pull_none>,
88 <3 RK_PD1 5 &pcfg_pull_none>,
90 <3 RK_PD2 5 &pcfg_pull_none>,
92 <3 RK_PD3 5 &pcfg_pull_none>,
94 <3 RK_PD4 5 &pcfg_pull_none>,
96 <3 RK_PD5 5 &pcfg_pull_none>;
100 bt1120_pins: bt1120-pins {
103 <3 RK_PA6 2 &pcfg_pull_none>,
105 <3 RK_PA1 2 &pcfg_pull_none>,
107 <3 RK_PA2 2 &pcfg_pull_none>,
109 <3 RK_PA3 2 &pcfg_pull_none>,
111 <3 RK_PA4 2 &pcfg_pull_none>,
113 <3 RK_PA5 2 &pcfg_pull_none>,
115 <3 RK_PA7 2 &pcfg_pull_none>,
117 <3 RK_PB0 2 &pcfg_pull_none>,
119 <3 RK_PB1 2 &pcfg_pull_none>,
121 <3 RK_PB2 2 &pcfg_pull_none>,
123 <3 RK_PB3 2 &pcfg_pull_none>,
125 <3 RK_PB4 2 &pcfg_pull_none>,
127 <3 RK_PB5 2 &pcfg_pull_none>,
129 <3 RK_PB6 2 &pcfg_pull_none>,
131 <3 RK_PC1 2 &pcfg_pull_none>,
133 <3 RK_PC2 2 &pcfg_pull_none>,
135 <3 RK_PC3 2 &pcfg_pull_none>;
139 cam_pins: cam-pins {
142 <4 RK_PA7 1 &pcfg_pull_none>,
144 <4 RK_PB0 1 &pcfg_pull_none>;
148 can0m0_pins: can0m0-pins {
155 can0m1_pins: can0m1-pins {
164 can1m0_pins: can1m0-pins {
167 <1 RK_PA0 3 &pcfg_pull_none>,
169 <1 RK_PA1 3 &pcfg_pull_none>;
171 can1m1_pins: can1m1-pins {
174 <4 RK_PC2 3 &pcfg_pull_none>,
176 <4 RK_PC3 3 &pcfg_pull_none>;
180 can2m0_pins: can2m0-pins {
183 <4 RK_PB4 3 &pcfg_pull_none>,
185 <4 RK_PB5 3 &pcfg_pull_none>;
187 can2m1_pins: can2m1-pins {
196 cif_dvp_ctl: cif-dvp_ctl {
199 <4 RK_PC1 1 &pcfg_pull_none>,
201 <4 RK_PC0 1 &pcfg_pull_none>,
203 <3 RK_PC6 1 &pcfg_pull_none>,
205 <3 RK_PC7 1 &pcfg_pull_none>,
207 <3 RK_PD0 1 &pcfg_pull_none>,
209 <3 RK_PD1 1 &pcfg_pull_none>,
211 <3 RK_PD2 1 &pcfg_pull_none>,
213 <3 RK_PD3 1 &pcfg_pull_none>,
215 <3 RK_PD4 1 &pcfg_pull_none>,
217 <3 RK_PD5 1 &pcfg_pull_none>,
219 <3 RK_PD6 1 &pcfg_pull_none>,
221 <3 RK_PD7 1 &pcfg_pull_none>,
223 <4 RK_PA0 1 &pcfg_pull_none>,
225 <4 RK_PA1 1 &pcfg_pull_none>,
227 <4 RK_PA2 1 &pcfg_pull_none>,
229 <4 RK_PA3 1 &pcfg_pull_none>,
231 <4 RK_PA4 1 &pcfg_pull_none>,
233 <4 RK_PA5 1 &pcfg_pull_none>,
235 <4 RK_PB6 1 &pcfg_pull_none>,
237 <4 RK_PB7 1 &pcfg_pull_none>;
241 clk32k_pins: clk32k-pins {
244 <0 RK_PB0 1 &pcfg_pull_none>,
248 <2 RK_PC6 1 &pcfg_pull_none>;
252 cpu_pins: cpu-pins {
259 ebc_pins: ebc-pins {
278 <3 RK_PC6 2 &pcfg_pull_none>,
280 <3 RK_PC7 2 &pcfg_pull_none>,
282 <3 RK_PD0 2 &pcfg_pull_none>,
284 <3 RK_PD1 2 &pcfg_pull_none>,
286 <3 RK_PD2 2 &pcfg_pull_none>,
288 <3 RK_PD3 2 &pcfg_pull_none>,
290 <3 RK_PD4 2 &pcfg_pull_none>,
292 <3 RK_PD5 2 &pcfg_pull_none>,
294 <3 RK_PD6 2 &pcfg_pull_none>,
296 <3 RK_PD7 2 &pcfg_pull_none>,
320 edpdpm0_pins: edpdpm0-pins {
323 <4 RK_PC4 1 &pcfg_pull_none>;
325 edpdpm1_pins: edpdpm1-pins {
332 emmc_rstnout: emmc-rstnout {
335 <1 RK_PC7 1 &pcfg_pull_none>;
337 emmc_bus8: emmc-bus8 {
340 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
342 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
344 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
346 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
348 <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
350 <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
352 <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
354 <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
356 emmc_clk: emmc-clk {
359 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
361 emmc_cmd: emmc-cmd {
364 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
366 emmc_datastrobe: emmc-datastrobe {
368 <1 RK_PC6 1 &pcfg_pull_none>;
372 eth0_clkout_pins: eth0-clkout-pins {
379 eth1m0_clkout_pins: eth1m0-clkout-pins {
382 <3 RK_PB0 3 &pcfg_pull_none>;
384 eth1m1_clkout_pins: eth1m1-clkout-pins {
387 <4 RK_PB3 3 &pcfg_pull_none>;
391 flash_pins: flash-pins {
394 <1 RK_PD0 2 &pcfg_pull_none>,
396 <1 RK_PC6 3 &pcfg_pull_none>,
398 <1 RK_PD3 2 &pcfg_pull_none>,
400 <1 RK_PD4 2 &pcfg_pull_none>,
402 <1 RK_PB4 2 &pcfg_pull_none>,
404 <1 RK_PB5 2 &pcfg_pull_none>,
406 <1 RK_PB6 2 &pcfg_pull_none>,
408 <1 RK_PB7 2 &pcfg_pull_none>,
410 <1 RK_PC0 2 &pcfg_pull_none>,
412 <1 RK_PC1 2 &pcfg_pull_none>,
414 <1 RK_PC2 2 &pcfg_pull_none>,
416 <1 RK_PC3 2 &pcfg_pull_none>,
418 <1 RK_PC5 2 &pcfg_pull_none>,
420 <1 RK_PD2 2 &pcfg_pull_none>,
422 <1 RK_PD1 2 &pcfg_pull_none>,
424 <0 RK_PA7 1 &pcfg_pull_none>,
426 <1 RK_PC7 3 &pcfg_pull_none>,
428 <1 RK_PC4 2 &pcfg_pull_none>;
432 fspi_pins: fspi-pins {
435 <1 RK_PD0 1 &pcfg_pull_none>,
437 <1 RK_PD3 1 &pcfg_pull_none>,
439 <1 RK_PD1 1 &pcfg_pull_none>,
441 <1 RK_PD2 1 &pcfg_pull_none>,
443 <1 RK_PC7 2 &pcfg_pull_none>,
445 <1 RK_PD4 1 &pcfg_pull_none>;
447 fspi_cs1: fspi-cs1 {
450 <1 RK_PC6 2 &pcfg_pull_up>;
454 gmac0_miim: gmac0-miim {
461 gmac0_clkinout: gmac0-clkinout {
466 gmac0_rx_er: gmac0-rx-er {
471 gmac0_rx_bus2: gmac0-rx-bus2 {
474 <2 RK_PB6 1 &pcfg_pull_none>,
480 gmac0_tx_bus2: gmac0-tx-bus2 {
483 <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
485 <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
487 <2 RK_PB5 1 &pcfg_pull_none>;
489 gmac0_rgmii_clk: gmac0-rgmii-clk {
496 gmac0_rgmii_bus: gmac0-rgmii-bus {
509 gmac1m0_miim: gmac1m0-miim {
512 <3 RK_PC4 3 &pcfg_pull_none>,
514 <3 RK_PC5 3 &pcfg_pull_none>;
516 gmac1m0_clkinout: gmac1m0-clkinout {
519 <3 RK_PC0 3 &pcfg_pull_none>;
521 gmac1m0_rx_er: gmac1m0-rx-er {
524 <3 RK_PB4 3 &pcfg_pull_none>;
526 gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
529 <3 RK_PB1 3 &pcfg_pull_none>,
531 <3 RK_PB2 3 &pcfg_pull_none>,
533 <3 RK_PB3 3 &pcfg_pull_none>;
535 gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
538 <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
540 <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
542 <3 RK_PB7 3 &pcfg_pull_none>;
544 gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
547 <3 RK_PA7 3 &pcfg_pull_none>,
549 <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
551 gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
554 <3 RK_PA4 3 &pcfg_pull_none>,
556 <3 RK_PA5 3 &pcfg_pull_none>,
558 <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
560 <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
562 gmac1m1_miim: gmac1m1-miim {
565 <4 RK_PB6 3 &pcfg_pull_none>,
567 <4 RK_PB7 3 &pcfg_pull_none>;
569 gmac1m1_clkinout: gmac1m1-clkinout {
572 <4 RK_PC1 3 &pcfg_pull_none>;
574 gmac1m1_rx_er: gmac1m1-rx-er {
577 <4 RK_PB2 3 &pcfg_pull_none>;
579 gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
582 <4 RK_PA7 3 &pcfg_pull_none>,
584 <4 RK_PB0 3 &pcfg_pull_none>,
586 <4 RK_PB1 3 &pcfg_pull_none>;
588 gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
591 <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
593 <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
595 <4 RK_PA6 3 &pcfg_pull_none>;
597 gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
600 <4 RK_PA3 3 &pcfg_pull_none>,
602 <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
604 gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
607 <4 RK_PA1 3 &pcfg_pull_none>,
609 <4 RK_PA2 3 &pcfg_pull_none>,
611 <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
613 <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
617 gpu_pins: gpu-pins {
626 hdmitxm0_cec: hdmitxm0-cec {
629 <4 RK_PD1 1 &pcfg_pull_none>;
631 hdmitxm1_cec: hdmitxm1-cec {
634 <0 RK_PC7 1 &pcfg_pull_none>;
636 hdmitx_scl: hdmitx-scl {
638 <4 RK_PC7 1 &pcfg_pull_none>;
640 hdmitx_sda: hdmitx-sda {
642 <4 RK_PD0 1 &pcfg_pull_none>;
646 i2c0_xfer: i2c0-xfer {
649 <0 RK_PB1 1 &pcfg_pull_none_smt>,
651 <0 RK_PB2 1 &pcfg_pull_none_smt>;
655 i2c1_xfer: i2c1-xfer {
658 <0 RK_PB3 1 &pcfg_pull_none_smt>,
660 <0 RK_PB4 1 &pcfg_pull_none_smt>;
664 i2c2m0_xfer: i2c2m0-xfer {
667 <0 RK_PB5 1 &pcfg_pull_none_smt>,
669 <0 RK_PB6 1 &pcfg_pull_none_smt>;
671 i2c2m1_xfer: i2c2m1-xfer {
674 <4 RK_PB5 1 &pcfg_pull_none_smt>,
676 <4 RK_PB4 1 &pcfg_pull_none_smt>;
680 i2c3m0_xfer: i2c3m0-xfer {
683 <1 RK_PA1 1 &pcfg_pull_none_smt>,
685 <1 RK_PA0 1 &pcfg_pull_none_smt>;
687 i2c3m1_xfer: i2c3m1-xfer {
690 <3 RK_PB5 4 &pcfg_pull_none_smt>,
692 <3 RK_PB6 4 &pcfg_pull_none_smt>;
696 i2c4m0_xfer: i2c4m0-xfer {
699 <4 RK_PB3 1 &pcfg_pull_none_smt>,
701 <4 RK_PB2 1 &pcfg_pull_none_smt>;
703 i2c4m1_xfer: i2c4m1-xfer {
712 i2c5m0_xfer: i2c5m0-xfer {
715 <3 RK_PB3 4 &pcfg_pull_none_smt>,
717 <3 RK_PB4 4 &pcfg_pull_none_smt>;
719 i2c5m1_xfer: i2c5m1-xfer {
730 <1 RK_PA6 1 &pcfg_pull_none>;
734 <1 RK_PA5 1 &pcfg_pull_none>;
738 <1 RK_PA2 1 &pcfg_pull_none>;
742 <1 RK_PA4 1 &pcfg_pull_none>;
746 <1 RK_PA3 1 &pcfg_pull_none>;
750 <1 RK_PB3 1 &pcfg_pull_none>;
754 <1 RK_PB2 2 &pcfg_pull_none>;
758 <1 RK_PB1 2 &pcfg_pull_none>;
762 <1 RK_PB0 2 &pcfg_pull_none>;
766 <1 RK_PA7 1 &pcfg_pull_none>;
770 <1 RK_PB0 1 &pcfg_pull_none>;
774 <1 RK_PB1 1 &pcfg_pull_none>;
778 <1 RK_PB2 1 &pcfg_pull_none>;
786 <3 RK_PD0 4 &pcfg_pull_none>;
790 <3 RK_PC6 4 &pcfg_pull_none>;
798 <3 RK_PC7 4 &pcfg_pull_none>;
802 <3 RK_PD2 4 &pcfg_pull_none>;
806 <3 RK_PD3 4 &pcfg_pull_none>;
810 <3 RK_PD4 4 &pcfg_pull_none>;
814 <3 RK_PD5 4 &pcfg_pull_none>;
818 <3 RK_PD1 4 &pcfg_pull_none>;
830 <3 RK_PC5 5 &pcfg_pull_none>;
866 <3 RK_PA0 5 &pcfg_pull_none>;
870 <3 RK_PC1 5 &pcfg_pull_none>;
874 <3 RK_PC2 5 &pcfg_pull_none>;
876 i2s1_sclkrxm: i2s1-sclkrxm {
878 <3 RK_PC3 5 &pcfg_pull_none>;
880 i2s1_sdo3m: i2s1-sdo3m {
888 <2 RK_PC0 1 &pcfg_pull_none>;
892 <2 RK_PC3 1 &pcfg_pull_none>;
896 <2 RK_PC1 1 &pcfg_pull_none>;
900 <2 RK_PB7 1 &pcfg_pull_none>;
904 <2 RK_PC2 1 &pcfg_pull_none>;
908 <2 RK_PC5 1 &pcfg_pull_none>;
912 <2 RK_PC4 1 &pcfg_pull_none>;
946 <3 RK_PA4 4 &pcfg_pull_none>;
950 <3 RK_PA2 4 &pcfg_pull_none>;
954 <3 RK_PA3 4 &pcfg_pull_none>;
958 <3 RK_PA6 4 &pcfg_pull_none>;
962 <3 RK_PA5 4 &pcfg_pull_none>;
986 isp_pins: isp-pins {
991 <4 RK_PA6 1 &pcfg_pull_none>,
993 <4 RK_PB1 1 &pcfg_pull_none>;
997 jtag_pins: jtag-pins {
1000 <1 RK_PD7 2 &pcfg_pull_none>,
1006 lcdc_ctl: lcdc-ctl {
1009 <3 RK_PA0 1 &pcfg_pull_none>,
1011 <2 RK_PD0 1 &pcfg_pull_none>,
1013 <2 RK_PD1 1 &pcfg_pull_none>,
1015 <2 RK_PD2 1 &pcfg_pull_none>,
1017 <2 RK_PD3 1 &pcfg_pull_none>,
1019 <2 RK_PD4 1 &pcfg_pull_none>,
1021 <2 RK_PD5 1 &pcfg_pull_none>,
1023 <2 RK_PD6 1 &pcfg_pull_none>,
1025 <2 RK_PD7 1 &pcfg_pull_none>,
1027 <3 RK_PA1 1 &pcfg_pull_none>,
1029 <3 RK_PA2 1 &pcfg_pull_none>,
1031 <3 RK_PA3 1 &pcfg_pull_none>,
1033 <3 RK_PA4 1 &pcfg_pull_none>,
1035 <3 RK_PA5 1 &pcfg_pull_none>,
1037 <3 RK_PA6 1 &pcfg_pull_none>,
1039 <3 RK_PA7 1 &pcfg_pull_none>,
1041 <3 RK_PB0 1 &pcfg_pull_none>,
1043 <3 RK_PB1 1 &pcfg_pull_none>,
1045 <3 RK_PB2 1 &pcfg_pull_none>,
1047 <3 RK_PB3 1 &pcfg_pull_none>,
1049 <3 RK_PB4 1 &pcfg_pull_none>,
1051 <3 RK_PB5 1 &pcfg_pull_none>,
1053 <3 RK_PB6 1 &pcfg_pull_none>,
1055 <3 RK_PB7 1 &pcfg_pull_none>,
1057 <3 RK_PC0 1 &pcfg_pull_none>,
1059 <3 RK_PC3 1 &pcfg_pull_none>,
1061 <3 RK_PC1 1 &pcfg_pull_none>,
1063 <3 RK_PC2 1 &pcfg_pull_none>;
1067 mcu_pins: mcu-pins {
1082 npu_pins: npu-pins {
1089 pcie20m0_pins: pcie20m0-pins {
1092 <0 RK_PA5 3 &pcfg_pull_none>,
1094 <0 RK_PB6 3 &pcfg_pull_none>,
1096 <0 RK_PB5 3 &pcfg_pull_none>;
1098 pcie20m1_pins: pcie20m1-pins {
1103 <3 RK_PC1 4 &pcfg_pull_none>,
1107 pcie20m2_pins: pcie20m2-pins {
1110 <1 RK_PB0 4 &pcfg_pull_none>,
1112 <1 RK_PB2 4 &pcfg_pull_none>,
1114 <1 RK_PB1 4 &pcfg_pull_none>;
1116 pcie20_buttonrstn: pcie20-buttonrstn {
1118 <0 RK_PB4 3 &pcfg_pull_none>;
1122 pcie30x1m0_pins: pcie30x1m0-pins {
1125 <0 RK_PA4 3 &pcfg_pull_none>,
1127 <0 RK_PC3 3 &pcfg_pull_none>,
1129 <0 RK_PC2 3 &pcfg_pull_none>;
1131 pcie30x1m1_pins: pcie30x1m1-pins {
1136 <3 RK_PA1 4 &pcfg_pull_none>,
1140 pcie30x1m2_pins: pcie30x1m2-pins {
1143 <1 RK_PA5 4 &pcfg_pull_none>,
1145 <1 RK_PA2 4 &pcfg_pull_none>,
1147 <1 RK_PA3 4 &pcfg_pull_none>;
1149 pcie30x1_buttonrstn: pcie30x1-buttonrstn {
1151 <0 RK_PB3 3 &pcfg_pull_none>;
1155 pcie30x2m0_pins: pcie30x2m0-pins {
1160 <0 RK_PC6 3 &pcfg_pull_none>,
1162 <0 RK_PC5 3 &pcfg_pull_none>;
1164 pcie30x2m1_pins: pcie30x2m1-pins {
1173 pcie30x2m2_pins: pcie30x2m2-pins {
1182 pcie30x2_buttonrstn: pcie30x2-buttonrstn {
1184 <0 RK_PB0 3 &pcfg_pull_none>;
1188 pdmm0_clk: pdmm0-clk {
1191 <1 RK_PA6 3 &pcfg_pull_none>;
1195 <1 RK_PA4 3 &pcfg_pull_none>;
1199 <1 RK_PB3 2 &pcfg_pull_none>;
1203 <1 RK_PB2 3 &pcfg_pull_none>;
1207 <1 RK_PB1 3 &pcfg_pull_none>;
1211 <1 RK_PB0 3 &pcfg_pull_none>;
1213 pdmm1_clk: pdmm1-clk {
1216 <3 RK_PD6 5 &pcfg_pull_none>;
1224 <3 RK_PD7 5 &pcfg_pull_none>;
1240 <3 RK_PC4 5 &pcfg_pull_none>;
1244 <3 RK_PB3 5 &pcfg_pull_none>;
1248 <3 RK_PB4 5 &pcfg_pull_none>;
1252 <3 RK_PB7 5 &pcfg_pull_none>;
1256 <3 RK_PC0 5 &pcfg_pull_none>;
1260 pmic_pins: pmic-pins {
1263 <0 RK_PA2 1 &pcfg_pull_none>;
1267 pmu_pins: pmu-pins {
1272 <0 RK_PA6 3 &pcfg_pull_none>,
1284 pwm0m0_pins: pwm0m0-pins {
1287 <0 RK_PB7 1 &pcfg_pull_none>;
1289 pwm0m1_pins: pwm0m1-pins {
1296 pwm1m0_pins: pwm1m0-pins {
1299 <0 RK_PC0 1 &pcfg_pull_none>;
1301 pwm1m1_pins: pwm1m1-pins {
1308 pwm2m0_pins: pwm2m0-pins {
1311 <0 RK_PC1 1 &pcfg_pull_none>;
1313 pwm2m1_pins: pwm2m1-pins {
1320 pwm3_pins: pwm3-pins {
1323 <0 RK_PC2 1 &pcfg_pull_none>;
1327 pwm4_pins: pwm4-pins {
1330 <0 RK_PC3 1 &pcfg_pull_none>;
1334 pwm5_pins: pwm5-pins {
1337 <0 RK_PC4 1 &pcfg_pull_none>;
1341 pwm6_pins: pwm6-pins {
1344 <0 RK_PC5 1 &pcfg_pull_none>;
1348 pwm7_pins: pwm7-pins {
1351 <0 RK_PC6 1 &pcfg_pull_none>;
1355 pwm8m0_pins: pwm8m0-pins {
1358 <3 RK_PB1 5 &pcfg_pull_none>;
1360 pwm8m1_pins: pwm8m1-pins {
1363 <1 RK_PD5 4 &pcfg_pull_none>;
1367 pwm9m0_pins: pwm9m0-pins {
1370 <3 RK_PB2 5 &pcfg_pull_none>;
1372 pwm9m1_pins: pwm9m1-pins {
1375 <1 RK_PD6 4 &pcfg_pull_none>;
1379 pwm10m0_pins: pwm10m0-pins {
1382 <3 RK_PB5 5 &pcfg_pull_none>;
1384 pwm10m1_pins: pwm10m1-pins {
1391 pwm11m0_pins: pwm11m0-pins {
1394 <3 RK_PB6 5 &pcfg_pull_none>;
1396 pwm11m1_pins: pwm11m1-pins {
1399 <4 RK_PC0 3 &pcfg_pull_none>;
1403 pwm12m0_pins: pwm12m0-pins {
1406 <3 RK_PB7 2 &pcfg_pull_none>;
1408 pwm12m1_pins: pwm12m1-pins {
1411 <4 RK_PC5 1 &pcfg_pull_none>;
1415 pwm13m0_pins: pwm13m0-pins {
1418 <3 RK_PC0 2 &pcfg_pull_none>;
1420 pwm13m1_pins: pwm13m1-pins {
1423 <4 RK_PC6 1 &pcfg_pull_none>;
1427 pwm14m0_pins: pwm14m0-pins {
1430 <3 RK_PC4 1 &pcfg_pull_none>;
1432 pwm14m1_pins: pwm14m1-pins {
1435 <4 RK_PC2 1 &pcfg_pull_none>;
1439 pwm15m0_pins: pwm15m0-pins {
1442 <3 RK_PC5 1 &pcfg_pull_none>;
1444 pwm15m1_pins: pwm15m1-pins {
1447 <4 RK_PC3 1 &pcfg_pull_none>;
1451 refclk_pins: refclk-pins {
1454 <0 RK_PA0 1 &pcfg_pull_none>;
1458 sata_pins: sata-pins {
1463 <0 RK_PA6 1 &pcfg_pull_none>,
1469 sata0_pins: sata0-pins {
1472 <4 RK_PC6 3 &pcfg_pull_none>;
1476 sata1_pins: sata1-pins {
1479 <4 RK_PC5 3 &pcfg_pull_none>;
1483 sata2_pins: sata2-pins {
1486 <4 RK_PC4 3 &pcfg_pull_none>;
1490 scr_pins: scr-pins {
1493 <1 RK_PA2 3 &pcfg_pull_none>,
1495 <1 RK_PA7 3 &pcfg_pull_none>,
1497 <1 RK_PA3 3 &pcfg_pull_none>,
1499 <1 RK_PA5 3 &pcfg_pull_none>;
1503 sdmmc0_bus4: sdmmc0-bus4 {
1506 <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
1508 <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
1510 <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
1512 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
1514 sdmmc0_clk: sdmmc0-clk {
1517 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
1519 sdmmc0_cmd: sdmmc0-cmd {
1522 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
1524 sdmmc0_det: sdmmc0-det {
1526 <0 RK_PA4 1 &pcfg_pull_up>;
1528 sdmmc0_pwren: sdmmc0-pwren {
1530 <0 RK_PA5 1 &pcfg_pull_none>;
1534 sdmmc1_bus4: sdmmc1-bus4 {
1537 <2 RK_PA3 1 &pcfg_pull_up_drv_level_5>,
1539 <2 RK_PA4 1 &pcfg_pull_up_drv_level_5>,
1541 <2 RK_PA5 1 &pcfg_pull_up_drv_level_5>,
1543 <2 RK_PA6 1 &pcfg_pull_up_drv_level_5>;
1545 sdmmc1_clk: sdmmc1-clk {
1548 <2 RK_PB0 1 &pcfg_pull_up_drv_level_5>;
1550 sdmmc1_cmd: sdmmc1-cmd {
1553 <2 RK_PA7 1 &pcfg_pull_up_drv_level_5>;
1555 sdmmc1_det: sdmmc1-det {
1557 <2 RK_PB2 1 &pcfg_pull_none>;
1559 sdmmc1_pwren: sdmmc1-pwren {
1561 <2 RK_PB1 1 &pcfg_pull_none>;
1565 sdmmc2m0_bus4: sdmmc2m0-bus4 {
1568 <3 RK_PC6 3 &pcfg_pull_up_drv_level_5>,
1570 <3 RK_PC7 3 &pcfg_pull_up_drv_level_5>,
1572 <3 RK_PD0 3 &pcfg_pull_up_drv_level_5>,
1574 <3 RK_PD1 3 &pcfg_pull_up_drv_level_5>;
1576 sdmmc2m0_clk: sdmmc2m0-clk {
1579 <3 RK_PD3 3 &pcfg_pull_up_drv_level_5>;
1581 sdmmc2m0_cmd: sdmmc2m0-cmd {
1584 <3 RK_PD2 3 &pcfg_pull_up_drv_level_5>;
1588 <3 RK_PD4 3 &pcfg_pull_none>;
1592 <3 RK_PD5 3 &pcfg_pull_none>;
1594 sdmmc2m1_bus4: sdmmc2m1-bus4 {
1597 <3 RK_PA1 5 &pcfg_pull_up_drv_level_5>,
1599 <3 RK_PA2 5 &pcfg_pull_up_drv_level_5>,
1601 <3 RK_PA3 5 &pcfg_pull_up_drv_level_5>,
1603 <3 RK_PA4 5 &pcfg_pull_up_drv_level_5>;
1605 sdmmc2m1_clk: sdmmc2m1-clk {
1608 <3 RK_PA6 5 &pcfg_pull_up_drv_level_5>;
1610 sdmmc2m1_cmd: sdmmc2m1-cmd {
1613 <3 RK_PA5 5 &pcfg_pull_up_drv_level_5>;
1617 <3 RK_PA7 4 &pcfg_pull_none>;
1621 <3 RK_PB0 4 &pcfg_pull_none>;
1625 spdifm0_pins: spdifm0-pins {
1628 <1 RK_PA4 4 &pcfg_pull_none>;
1630 spdifm1_pins: spdifm1-pins {
1633 <3 RK_PC5 2 &pcfg_pull_none>;
1635 spdifm2_pins: spdifm2-pins {
1662 spi0clkm0_hs: spi0clkm0-hs {
1666 spi0misom0_hs: spi0misom0-hs {
1670 spi0mosim0_hs: spi0mosim0-hs {
1676 <2 RK_PD3 3 &pcfg_pull_none>;
1680 <2 RK_PD2 3 &pcfg_pull_none>;
1684 <2 RK_PD0 3 &pcfg_pull_none>;
1688 <2 RK_PD1 3 &pcfg_pull_none>;
1690 spi0clkm1_hs: spi0clkm1-hs {
1692 <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>;
1694 spi0misom1_hs: spi0misom1-hs {
1696 <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>;
1698 spi0mosim1_hs: spi0mosim1-hs {
1700 <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
1706 <2 RK_PB5 3 &pcfg_pull_none>;
1714 <2 RK_PC6 3 &pcfg_pull_none>;
1718 <2 RK_PB6 3 &pcfg_pull_none>;
1724 spi1clkm0_hs: spi1clkm0-hs {
1726 <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>;
1728 spi1misom0_hs: spi1misom0-hs {
1730 <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>;
1732 spi1mosim0_hs: spi1mosim0-hs {
1738 <3 RK_PC3 3 &pcfg_pull_none>;
1742 <3 RK_PA1 3 &pcfg_pull_none>;
1746 <3 RK_PC2 3 &pcfg_pull_none>;
1750 <3 RK_PC1 3 &pcfg_pull_none>;
1752 spi1clkm1_hs: spi1clkm1-hs {
1754 <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>;
1756 spi1misom1_hs: spi1misom1-hs {
1758 <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>;
1760 spi1mosim1_hs: spi1mosim1-hs {
1762 <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
1786 spi2clkm0_hs: spi2clkm0-hs {
1790 spi2misom0_hs: spi2misom0-hs {
1794 spi2mosim0_hs: spi2mosim0-hs {
1800 <3 RK_PA0 3 &pcfg_pull_none>;
1804 <2 RK_PD5 3 &pcfg_pull_none>;
1808 <2 RK_PD4 3 &pcfg_pull_none>;
1812 <2 RK_PD7 3 &pcfg_pull_none>;
1816 <2 RK_PD6 3 &pcfg_pull_none>;
1818 spi2clkm1_hs: spi2clkm1-hs {
1820 <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>;
1822 spi2misom1_hs: spi2misom1-hs {
1824 <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>;
1826 spi2mosim1_hs: spi2mosim1-hs {
1828 <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
1852 spi3clkm0_hs: spi3clkm0-hs {
1856 spi3misom0_hs: spi3misom0-hs {
1860 spi3mosim0_hs: spi3mosim0-hs {
1884 spi3clkm1_hs: spi3clkm1-hs {
1888 spi3misom1_hs: spi3misom1-hs {
1892 spi3mosim1_hs: spi3mosim1-hs {
1898 tsadc_gpio: tsadc-gpio {
1901 tsadcm0_pins: tsadcm0-pins {
1904 <0 RK_PA1 1 &pcfg_pull_none>;
1906 tsadcm1_pins: tsadcm1-pins {
1911 tsadc_shutorg: tsadc-shutorg {
1917 uart0_xfer: uart0-xfer {
1920 <0 RK_PC0 3 &pcfg_pull_up>,
1922 <0 RK_PC1 3 &pcfg_pull_up>;
1924 uart0_ctsn: uart0-ctsn {
1926 <0 RK_PC7 3 &pcfg_pull_none>;
1928 uart0_rtsn: uart0-rtsn {
1930 <0 RK_PC4 3 &pcfg_pull_none>;
1934 uart1m0_xfer: uart1m0-xfer {
1949 uart1m1_xfer: uart1m1-xfer {
1952 <3 RK_PD7 4 &pcfg_pull_up>,
1954 <3 RK_PD6 4 &pcfg_pull_up>;
1966 uart2m0_xfer: uart2m0-xfer {
1969 <0 RK_PD0 1 &pcfg_pull_up>,
1971 <0 RK_PD1 1 &pcfg_pull_up>;
1973 uart2m1_xfer: uart2m1-xfer {
1976 <1 RK_PD6 2 &pcfg_pull_up>,
1978 <1 RK_PD5 2 &pcfg_pull_up>;
1982 uart3m0_xfer: uart3m0-xfer {
1985 <1 RK_PA0 2 &pcfg_pull_up>,
1987 <1 RK_PA1 2 &pcfg_pull_up>;
1991 <1 RK_PA3 2 &pcfg_pull_none>;
1995 <1 RK_PA2 2 &pcfg_pull_none>;
1997 uart3m1_xfer: uart3m1-xfer {
2000 <3 RK_PC0 4 &pcfg_pull_up>,
2002 <3 RK_PB7 4 &pcfg_pull_up>;
2006 uart4m0_xfer: uart4m0-xfer {
2009 <1 RK_PA4 2 &pcfg_pull_up>,
2011 <1 RK_PA6 2 &pcfg_pull_up>;
2015 <1 RK_PA7 2 &pcfg_pull_none>;
2019 <1 RK_PA5 2 &pcfg_pull_none>;
2021 uart4m1_xfer: uart4m1-xfer {
2024 <3 RK_PB1 4 &pcfg_pull_up>,
2026 <3 RK_PB2 4 &pcfg_pull_up>;
2030 uart5m0_xfer: uart5m0-xfer {
2033 <2 RK_PA1 3 &pcfg_pull_up>,
2035 <2 RK_PA2 3 &pcfg_pull_up>;
2039 <1 RK_PD7 3 &pcfg_pull_none>;
2043 <2 RK_PA0 3 &pcfg_pull_none>;
2045 uart5m1_xfer: uart5m1-xfer {
2048 <3 RK_PC3 4 &pcfg_pull_up>,
2050 <3 RK_PC2 4 &pcfg_pull_up>;
2054 uart6m0_xfer: uart6m0-xfer {
2057 <2 RK_PA3 3 &pcfg_pull_up>,
2059 <2 RK_PA4 3 &pcfg_pull_up>;
2063 <2 RK_PC0 3 &pcfg_pull_none>;
2067 <2 RK_PB7 3 &pcfg_pull_none>;
2069 uart6m1_xfer: uart6m1-xfer {
2072 <1 RK_PD6 3 &pcfg_pull_up>,
2074 <1 RK_PD5 3 &pcfg_pull_up>;
2078 uart7m0_xfer: uart7m0-xfer {
2081 <2 RK_PA5 3 &pcfg_pull_up>,
2083 <2 RK_PA6 3 &pcfg_pull_up>;
2087 <2 RK_PC2 3 &pcfg_pull_none>;
2091 <2 RK_PC1 3 &pcfg_pull_none>;
2093 uart7m1_xfer: uart7m1-xfer {
2096 <3 RK_PC5 4 &pcfg_pull_up>,
2098 <3 RK_PC4 4 &pcfg_pull_up>;
2100 uart7m2_xfer: uart7m2-xfer {
2109 uart8m0_xfer: uart8m0-xfer {
2114 <2 RK_PC5 3 &pcfg_pull_up>;
2118 <2 RK_PB2 3 &pcfg_pull_none>;
2122 <2 RK_PB1 3 &pcfg_pull_none>;
2124 uart8m1_xfer: uart8m1-xfer {
2127 <3 RK_PA0 4 &pcfg_pull_up>,
2133 uart9m0_xfer: uart9m0-xfer {
2136 <2 RK_PA7 3 &pcfg_pull_up>,
2138 <2 RK_PB0 3 &pcfg_pull_up>;
2142 <2 RK_PC4 3 &pcfg_pull_none>;
2146 <2 RK_PC3 3 &pcfg_pull_none>;
2148 uart9m1_xfer: uart9m1-xfer {
2155 uart9m2_xfer: uart9m2-xfer {
2164 vopm0_pins: vopm0-pins {
2169 vopm1_pins: vopm1-pins {
2172 <3 RK_PC4 2 &pcfg_pull_none>;
2175 gmac-txd-level3 {
2176 gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
2179 <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
2181 <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
2183 <2 RK_PB5 1 &pcfg_pull_none>;
2185 gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
2196 gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
2199 <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
2201 <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
2203 <3 RK_PB7 3 &pcfg_pull_none>;
2205 gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
2208 <3 RK_PA4 3 &pcfg_pull_none>,
2210 <3 RK_PA5 3 &pcfg_pull_none>,
2212 <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
2214 <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
2216 gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
2219 <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
2221 <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
2223 <4 RK_PA6 3 &pcfg_pull_none>;
2225 gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
2228 <4 RK_PA1 3 &pcfg_pull_none>,
2230 <4 RK_PA2 3 &pcfg_pull_none>,
2232 <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
2234 <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
2237 gmac-txc-level2 {
2238 gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
2245 gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
2248 <3 RK_PA7 3 &pcfg_pull_none>,
2250 <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
2252 gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
2255 <4 RK_PA3 3 &pcfg_pull_none>,
2257 <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;