Lines Matching full:cru
6 #include <dt-bindings/clock/rk3562-cru.h>
87 clocks = <&cru ACLK_ISP>;
96 clocks = <&cru ACLK_TOP_VIO>;
105 clocks = <&cru ACLK_TOP_VIO>;
114 clocks = <&cru ACLK_TOP_VIO>;
123 clocks = <&cru ACLK_VOP>;
138 clocks = <&cru ARMCLK>;
146 clocks = <&cru ARMCLK>;
154 clocks = <&cru ARMCLK>;
162 clocks = <&cru ARMCLK>;
473 clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>,
474 <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>;
490 resets = <&cru SRST_USB3OTG>;
520 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
532 clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
789 cru: clock-controller@ff100000 { label
790 compatible = "rockchip,rk3562-cru";
797 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
798 <&cru ARMCLK>;
807 clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>;
821 clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>;
835 clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>;
851 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
862 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
873 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
886 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
955 clocks = <&cru PCLK_PMU1_MAILBOX>;
965 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
967 assigned-clocks = <&cru ACLK_RKNN>;
969 resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>;
981 clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
1000 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>;
1031 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
1034 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
1036 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
1037 <&cru SRST_RKVDEC_HEVC_CA>;
1053 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1065 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1068 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
1069 <&cru SRST_RKVENC_CORE>;
1071 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1086 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
1100 clocks = <&cru PCLK_CSIHOST0>;
1102 resets = <&cru SRST_P_CSIHOST0>;
1114 clocks = <&cru PCLK_CSIHOST1>;
1116 resets = <&cru SRST_P_CSIHOST1>;
1128 clocks = <&cru PCLK_CSIHOST2>;
1130 resets = <&cru SRST_P_CSIHOST2>;
1142 clocks = <&cru PCLK_CSIHOST3>;
1144 resets = <&cru SRST_P_CSIHOST3>;
1152 clocks = <&cru PCLK_CSIPHY0>;
1154 resets = <&cru SRST_P_CSIPHY0>;
1163 clocks = <&cru PCLK_CSIPHY1>;
1165 resets = <&cru SRST_P_CSIPHY1>;
1177 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>;
1179 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>,
1180 <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>,
1181 <&cru SRST_I3_VICAP>;
1196 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1211 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
1223 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
1236 clocks = <&cru ACLK_VOP>,
1237 <&cru HCLK_VOP>,
1238 <&cru DCLK_VOP>,
1239 <&cru DCLK_VOP1>;
1244 resets = <&cru SRST_A_VOP>,
1245 <&cru SRST_H_VOP>,
1246 <&cru SRST_D_VOP>,
1247 <&cru SRST_D_VOP1>;
1310 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1323 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
1335 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
1346 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1349 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
1365 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1376 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
1377 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
1378 <&cru CLK_PCIE20_AUX>;
1410 resets = <&cru SRST_PCIE20_POWERUP>;
1428 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1444 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1458 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1470 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1482 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1506 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1518 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1530 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1542 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1554 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1568 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1579 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1590 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1603 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1614 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1625 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1636 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1649 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1660 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1671 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1682 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1695 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1705 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1707 resets = <&cru SRST_P_SARADC>;
1715 clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>;
1743 clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>,
1744 <&cru PCLK_PHP>;
1746 assigned-clocks = <&cru CLK_PIPEPHY_REF>;
1748 resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>;
1759 clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>;
1763 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
1781 clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>;
1785 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
1806 clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>;
1810 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
1824 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1846 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
1856 clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>;
1858 resets = <&cru SRST_DSM>;
1872 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1874 assigned-clocks = <&cru SCLK_SFC>;
1885 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
1887 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1888 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1889 <&cru TMCLK_EMMC>;
1891 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1892 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1893 <&cru SRST_T_EMMC>;
1905 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>,
1906 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1908 resets = <&cru SRST_H_SDMMC0>;
1920 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>,
1921 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1923 resets = <&cru SRST_H_SDMMC1>;
1939 resets = <&cru SRST_CORE_CRYPTO>;
1950 resets = <&cru SRST_H_RK_RNG_NS>;
1960 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
1961 <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>,
1962 <&cru PCLK_OTPPHY>;
1964 resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
1965 <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>,
1966 <&cru SRST_P_OTPPHY>;
1999 clocks = <&cru ACLK_DMAC>;
2015 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2028 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2041 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2054 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2067 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2080 clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>;
2091 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
2093 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
2095 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>;
2099 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2112 clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
2113 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
2116 resets = <&cru SRST_A_GMAC>;
2155 clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>;
2157 resets = <&cru SRST_P_SARADC_VCCIO156>;
2167 clocks = <&cru PCLK_MAILBOX>;
2177 clocks = <&cru PCLK_DSITX>;
2179 resets = <&cru SRST_P_DSITX>;
2218 clocks = <&cru CLK_MIPIDSIPHY_REF>,
2219 <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>;
2222 resets = <&cru SRST_P_DSIPHY>;
2236 clocks = <&cru CLK_GMAC_50M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
2237 <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
2240 resets = <&cru SRST_A_MAC100>;
2262 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
2275 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
2288 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
2301 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
2314 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;