Lines Matching full:cru
6 #include <dt-bindings/clock/rk3528-cru.h>
359 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
360 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
361 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
362 <&cru PCLK_PCIE_PHY>;
396 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
397 <&cru SRST_PRESETN_CRU_PCIE>;
412 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
413 <&cru ACLK_USB3OTG>;
429 resets = <&cru SRST_ARESETN_USB3OTG>;
459 clocks = <&cru HCLK_USBHOST>,
460 <&cru HCLK_USBHOST_ARB>,
472 clocks = <&cru HCLK_USBHOST>,
473 <&cru HCLK_USBHOST_ARB>,
667 compatible = "rockchip,rk3528-grf-cru";
686 cru: clock-controller@ff4a0000 { label
687 compatible = "rockchip,rk3528-cru";
694 <&cru XIN_OSC0_DIV>,
695 <&cru PLL_GPLL>,
696 <&cru PLL_PPLL>,
697 <&cru PLL_CPLL>,
698 <&cru ARMCLK>,
699 <&cru CLK_MATRIX_250M_SRC>,
700 <&cru CLK_MATRIX_500M_SRC>,
701 <&cru CLK_MATRIX_50M_SRC>,
702 <&cru CLK_MATRIX_100M_SRC>,
703 <&cru CLK_MATRIX_150M_SRC>,
704 <&cru CLK_MATRIX_200M_SRC>,
705 <&cru CLK_MATRIX_300M_SRC>,
706 <&cru CLK_MATRIX_339M_SRC>,
707 <&cru CLK_MATRIX_400M_SRC>,
708 <&cru CLK_MATRIX_600M_SRC>,
709 <&cru CLK_PPLL_50M_MATRIX>,
710 <&cru CLK_PPLL_100M_MATRIX>,
711 <&cru CLK_PPLL_125M_MATRIX>,
712 <&cru ACLK_BUS_VOPGL_ROOT>;
755 clocks = <&cru ACLK_GPU_MALI>,
756 <&cru PCLK_GPU_ROOT>;
781 clocks = <&cru PCLK_PMU_MAILBOX>;
805 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>,
806 <&cru PCLK_GPU_ROOT>;
886 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
889 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
891 resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>,
892 <&cru SRST_RESETN_HEVC_CA_RKVDEC>;
908 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
920 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
923 resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>,
924 <&cru SRST_RESETN_CORE_RKVENC>;
926 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
941 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
953 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
955 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
971 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
982 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
984 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
1003 clocks = <&cru ACLK_VOP>,
1004 <&cru HCLK_VOP>,
1005 <&cru DCLK_VOP0>,
1006 <&cru DCLK_VOP1>;
1011 assigned-clocks = <&cru DCLK_VOP0>;
1050 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1063 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
1074 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>;
1084 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1087 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1089 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1090 <&cru SRST_RESETN_CORE_VDPP>;
1105 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>;
1117 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1120 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1122 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1123 <&cru SRST_RESETN_CORE_VDPP>;
1137 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1140 resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>;
1156 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1167 clocks = <&cru HCLK_CVBS>,
1168 <&cru PCLK_VCDCPHY>,
1169 <&cru DCLK_CVBS>,
1170 <&cru DCLK_4X_CVBS>;
1209 clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>,
1210 <&cru HCLK_HDCP>;
1221 clocks = <&cru PCLK_HDMI>,
1222 <&cru CLK_SFR_HDMI>,
1223 <&cru CLK_CEC_HDMI>;
1257 assigned-clocks = <&cru CLK_CAN0>;
1259 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
1261 resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_PRESETN_CAN0>;
1270 assigned-clocks = <&cru CLK_CAN1>;
1272 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
1274 resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_PRESETN_CAN1>;
1283 assigned-clocks = <&cru CLK_CAN2>;
1285 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
1287 resets = <&cru SRST_RESETN_CAN2>, <&cru SRST_PRESETN_CAN2>;
1296 assigned-clocks = <&cru CLK_CAN3>;
1298 clocks = <&cru CLK_CAN3>, <&cru PCLK_CAN3>;
1300 resets = <&cru SRST_RESETN_CAN3>, <&cru SRST_PRESETN_CAN3>;
1311 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1326 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1339 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1351 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1363 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1375 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1387 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1399 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1411 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1423 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1434 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
1447 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1460 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1473 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1486 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1499 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1512 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1525 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1541 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1552 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1563 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1576 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1587 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1598 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1609 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1622 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1631 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
1638 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1649 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
1651 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
1653 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
1657 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1667 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1669 resets = <&cru SRST_PRESETN_SARADC>;
1678 clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>;
1682 resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>;
1692 clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>;
1696 resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
1708 clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>;
1712 resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>;
1722 clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>;
1726 resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
1737 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1759 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
1773 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
1774 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
1775 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
1779 resets = <&cru SRST_ARESETN_MAC_VO>;
1804 clocks = <&cru CLK_MACPHY>;
1805 resets = <&cru SRST_RESETN_MACPHY>;
1838 clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
1839 <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
1842 resets = <&cru SRST_ARESETN_MAC>;
1881 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1883 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
1884 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1885 <&cru TCLK_EMMC>;
1887 resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>,
1888 <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>,
1889 <&cru SRST_TRESETN_EMMC>;
1899 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1901 assigned-clocks = <&cru SCLK_SFC>;
1914 clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>,
1918 resets = <&cru SRST_HRESETN_SDIO0>;
1930 clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>,
1934 resets = <&cru SRST_HRESETN_SDIO1>;
1946 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>,
1950 resets = <&cru SRST_HRESETN_SDMMC0>;
1967 resets = <&cru SRST_RESETN_CORE_CRYPTO>;
1978 resets = <&cru SRST_HRESETN_TRNG_NS>;
1988 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
1989 <&cru PCLK_OTPC_NS>;
1991 resets = <&cru SRST_RESETN_USER_OTPC_NS>,
1992 <&cru SRST_RESETN_SBPI_OTPC_NS>,
1993 <&cru SRST_PRESETN_OTPC_NS>;
2036 clocks = <&cru ACLK_DMAC>;
2053 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>;
2055 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
2057 resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>;
2067 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
2097 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
2108 clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
2110 resets = <&cru SRST_PRESETN_ACODEC>;
2126 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2138 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2150 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2162 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2174 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;