Lines Matching +full:0 +full:xff200000
57 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
99 reg = <0x0 0x2>;
109 reg = <0x0 0x3>;
122 arm,psci-suspend-param = <0x0010000>;
132 arm,psci-suspend-param = <0x0010000>;
149 0 1310 0
158 rockchip,pvtm-offset = <0x18>;
163 rockchip,pvtm-temp-prop = <0 0>;
270 arm,smc-id = <0x82000010>;
272 #size-cells = <0>;
275 reg = <0x14>;
296 rockchip,sleep-debug-en = <0>;
298 (0
303 (0
321 thermal-sensors = <&tsadc 0>;
344 #clock-cells = <0>;
351 reg = <0x0 0x0010f000 0x0 0x100>;
358 bus-range = <0x0 0xff>;
376 interrupt-map-mask = <0 0 0 7>;
377 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
378 <0 0 0 2 &pcie2x1_intc 1>,
379 <0 0 0 3 &pcie2x1_intc 2>,
380 <0 0 0 4 &pcie2x1_intc 3>;
381 linux,pci-domain = <0>;
389 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
390 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
391 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
392 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
393 reg = <0x0 0xfe4f0000 0x0 0x10000>,
394 <0x1 0x40000000 0x0 0x400000>;
403 #address-cells = <0>;
423 reg = <0x0 0xfe500000 0x0 0x400000>;
446 #address-cells = <0>;
448 reg = <0x0 0xfed01000 0 0x1000>,
449 <0x0 0xfed02000 0 0x2000>,
450 <0x0 0xfed04000 0 0x2000>,
451 <0x0 0xfed06000 0 0x2000>;
457 reg = <0x0 0xff100000 0x0 0x40000>;
470 reg = <0x0 0xff140000 0x0 0x40000>;
483 reg = <0x0 0xff190000 0x0 0x1000>,
484 <0x0 0xff192000 0x0 0x1000>,
485 <0x0 0xff194000 0x0 0x1000>,
486 <0x0 0xff196000 0x0 0x1000>;
491 reg = <0x0 0xff200000 0x0 0x20>;
496 reg = <0x0 0xff200080 0x0 0x20>;
501 reg = <0x0 0xff200100 0x0 0x20>;
506 reg = <0x0 0xff200200 0x0 0x20>;
511 reg = <0x0 0xff200280 0x0 0x20>;
516 reg = <0x0 0xff200300 0x0 0x20>;
521 reg = <0x0 0xff200380 0x0 0x20>;
526 reg = <0x0 0xff210000 0x0 0x20>;
531 reg = <0x0 0xff210080 0x0 0x20>;
536 reg = <0x0 0xff220000 0x0 0x20>;
541 reg = <0x0 0xff220080 0x0 0x20>;
546 reg = <0x0 0xff240000 0x0 0x20>;
551 reg = <0x0 0xff250000 0x0 0x20>;
556 reg = <0x0 0xff260000 0x0 0x20>;
561 reg = <0x0 0xff270000 0x0 0x20>;
566 reg = <0x0 0xff270080 0x0 0x20>;
571 reg = <0x0 0xff270100 0x0 0x20>;
576 reg = <0x0 0xff270200 0x0 0x20>;
581 reg = <0x0 0xff270280 0x0 0x20>;
586 reg = <0x0 0xff270300 0x0 0x20>;
591 reg = <0x0 0xff270380 0x0 0x20>;
596 reg = <0x0 0xff270480 0x0 0x20>;
601 reg = <0x0 0xff270500 0x0 0x20>;
606 reg = <0x0 0xff280000 0x0 0x20>;
611 reg = <0x0 0xff280080 0x0 0x20>;
616 reg = <0x0 0xff280100 0x0 0x20>;
621 reg = <0x0 0xff280180 0x0 0x20>;
626 reg = <0x0 0xff280200 0x0 0x20>;
631 reg = <0x0 0xff280280 0x0 0x20>;
636 reg = <0x0 0xff280300 0x0 0x20>;
641 reg = <0x0 0xff280380 0x0 0x20>;
646 reg = <0x0 0xff280400 0x0 0x20>;
651 * CORE_GRF: 0xff300000
652 * GPU_GRF: 0xff310000
653 * RKVENC_GRF: 0xff320000
654 * DDR_GRF: 0xff330000
655 * VPU_GRF: 0xff340000
656 * COMBO_PIPE_PHY_GRF: 0xff348000
657 * RKVDEC_GRF: 0xff350000
658 * VO_GRF: 0xff360000
659 * PMU_GRF: 0xff370000
660 * SYS_GRF: 0xff380000
664 reg = <0x0 0xff300000 0x0 0x90000>;
673 offset = <0x70200>;
688 reg = <0x0 0xff4a0000 0x0 0x30000>;
738 reg = <0x0 0xff540000 0x0 0x40000>;
743 reg = <0x0 0xff600000 0x0 0x2000>;
749 #size-cells = <0>;
779 reg = <0x0 0xff630000 0x0 0x200>;
789 reg = <0x0 0xff700000 0x0 0x40000>;
832 0 820 0
840 rockchip,pvtm-offset = <0x10018>;
845 rockchip,pvtm-temp-prop = <0 0>;
882 reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>;
888 rockchip,normal-rates = <340000000>, <0>, <600000000>;
897 rockchip,taskqueue-node = <0>;
898 rockchip,resetgroup-node = <0>;
905 reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>;
911 #iommu-cells = <0>;
917 reg = <0x0 0xff780000 0x0 0x6000>;
922 rockchip,normal-rates = <300000000>, <0>, <300000000>;
938 reg = <0x0 0xff78f000 0x0 0x40>;
944 #iommu-cells = <0>;
950 reg = <0x0 0xff7c0400 0x0 0x400>;
967 reg = <0x0 0xff7c0800 0x0 0x40>;
973 #iommu-cells = <0>;
979 reg = <0x0 0xff7c1000 0x0 0x200>;
996 reg = <0x0 0xff840000 0x0 0x3000>,
997 <0x0 0xff845000 0x0 0x1000>,
998 <0x0 0xff846400 0x0 0x800>;
1019 #size-cells = <0>;
1021 port@0 {
1023 #size-cells = <0>;
1024 reg = <0>;
1026 vp0_out_hdmi: endpoint@0 {
1027 reg = <0>;
1034 #size-cells = <0>;
1037 vp1_out_tve: endpoint@0 {
1038 reg = <0>;
1047 reg = <0x0 0xff847e00 0x0 0x100>;
1052 #iommu-cells = <0>;
1060 reg = <0x0 0xff850000 0x0 0x1000>;
1071 reg = <0x0 0xff850f00 0x0 0x100>;
1076 #iommu-cells = <0>;
1082 reg = <0x0 0xff860000 0x0 0x500>;
1086 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1102 reg = <0x0 0xff860800 0x0 0x100>;
1107 #iommu-cells = <0>;
1114 reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>;
1119 rockchip,normal-rates = <340000000>, <0>, <340000000>;
1135 reg = <0x0 0xff870000 0x0 0x400>;
1152 reg = <0x0 0xff870480 0x0 0x40>;
1158 #iommu-cells = <0>;
1164 reg = <0x0 0xff880000 0x0 0x4000>,
1165 <0x0 0xffde0000 0x0 0x300>;
1175 rockchip,lumafilter0 = <0x000a0ffa>;
1176 rockchip,lumafilter1 = <0x0ff4001a>;
1177 rockchip,lumafilter2 = <0x00110fd2>;
1178 rockchip,lumafilter3 = <0x0fe80051>;
1179 rockchip,lumafilter4 = <0x001a0f74>;
1180 rockchip,lumafilter5 = <0x0fe600ec>;
1181 rockchip,lumafilter6 = <0x0ffa0e43>;
1182 rockchip,lumafilter7 = <0x08200527>;
1189 #size-cells = <0>;
1191 port@0 {
1192 reg = <0>;
1194 #size-cells = <0>;
1196 tve_in_vp1: endpoint@0 {
1197 reg = <0>;
1207 reg = <0x0 0xff8c0000 0x0 0x2000>;
1217 reg = <0x0 0xff8d0000 0x0 0x20000>,
1218 <0x0 0xff610000 0x0 0x200>;
1228 pinctrl-0 = <&hdmi_pins>;
1231 #sound-dai-cells = <0>;
1237 #size-cells = <0>;
1239 port@0 {
1240 reg = <0>;
1242 #size-cells = <0>;
1244 hdmi_in_vp0: endpoint@0 {
1245 reg = <0>;
1255 reg = <0x0 0xff960000 0x0 0x100>;
1268 reg = <0x0 0xff970000 0x0 0x100>;
1281 reg = <0x0 0xff980000 0x0 0x100>;
1294 reg = <0x0 0xff990000 0x0 0x100>;
1307 reg = <0x0 0xff9c0000 0x0 0x1000>;
1310 #size-cells = <0>;
1316 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
1322 reg = <0x0 0xff9d0000 0x0 0x1000>;
1325 #size-cells = <0>;
1331 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
1337 reg = <0x0 0xff9f0000 0x0 0x100>;
1349 reg = <0x0 0xff9f8000 0x0 0x100>;
1361 reg = <0x0 0xffa00000 0x0 0x100>;
1373 reg = <0x0 0xffa08000 0x0 0x100>;
1385 reg = <0x0 0xffa10000 0x0 0x100>;
1397 reg = <0x0 0xffa18000 0x0 0x100>;
1409 reg = <0x0 0xffa20000 0x0 0x100>;
1421 reg = <0x0 0xffa28000 0x0 0x100>;
1433 reg = <0x0 0xffa50000 0x0 0x1000>;
1438 pinctrl-0 = <&i2c0m0_xfer>;
1440 #size-cells = <0>;
1446 reg = <0x0 0xffa58000 0x0 0x1000>;
1451 pinctrl-0 = <&i2c1m0_xfer>;
1453 #size-cells = <0>;
1459 reg = <0x0 0xffa60000 0x0 0x1000>;
1464 pinctrl-0 = <&i2c2m0_xfer>;
1466 #size-cells = <0>;
1472 reg = <0x0 0xffa68000 0x0 0x1000>;
1477 pinctrl-0 = <&i2c3m0_xfer>;
1479 #size-cells = <0>;
1485 reg = <0x0 0xffa70000 0x0 0x1000>;
1490 pinctrl-0 = <&i2c4_xfer>;
1492 #size-cells = <0>;
1498 reg = <0x0 0xffa78000 0x0 0x1000>;
1503 pinctrl-0 = <&i2c5m0_xfer>;
1505 #size-cells = <0>;
1511 reg = <0x0 0xffa80000 0x0 0x1000>;
1516 pinctrl-0 = <&i2c6m0_xfer>;
1518 #size-cells = <0>;
1524 reg = <0x0 0xffa88000 0x0 0x1000>;
1529 pinctrl-0 = <&i2c7_xfer>;
1531 #size-cells = <0>;
1537 reg = <0x0 0xffa90000 0x0 0x10>;
1540 pinctrl-0 = <&pwm0m0_pins>;
1548 reg = <0x0 0xffa90010 0x0 0x10>;
1551 pinctrl-0 = <&pwm1m0_pins>;
1559 reg = <0x0 0xffa90020 0x0 0x10>;
1562 pinctrl-0 = <&pwm2m0_pins>;
1570 reg = <0x0 0xffa90030 0x0 0x10>;
1575 pinctrl-0 = <&pwm3m0_pins>;
1583 reg = <0x0 0xffa98000 0x0 0x10>;
1586 pinctrl-0 = <&pwm4m0_pins>;
1594 reg = <0x0 0xffa98010 0x0 0x10>;
1597 pinctrl-0 = <&pwm5m0_pins>;
1605 reg = <0x0 0xffa98020 0x0 0x10>;
1608 pinctrl-0 = <&pwm6m0_pins>;
1616 reg = <0x0 0xffa98030 0x0 0x10>;
1621 pinctrl-0 = <&pwm7m0_pins>;
1629 reg = <0x0 0xffab0000 0x0 0x20>;
1637 reg = <0x0 0xffac0000 0x0 0x100>;
1646 reg = <0x0 0xffad0000 0x0 0x400>;
1657 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1658 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1664 reg = <0x0 0xffae0000 0x0 0x10000>;
1676 reg = <0x0 0xffb70000 0x0 0x1000>;
1684 #sound-dai-cells = <0>;
1690 reg = <0x0 0xffb80000 0x0 0x1000>;
1694 dmas = <&dmac 1>, <&dmac 0>;
1699 pinctrl-0 = <&i2s0m0_pins>;
1700 #sound-dai-cells = <0>;
1706 reg = <0x0 0xffb90000 0x0 0x1000>;
1714 #sound-dai-cells = <0>;
1720 reg = <0x0 0xffba0000 0x0 0x1000>;
1729 pinctrl-0 = <&i2s1_pins>;
1730 #sound-dai-cells = <0>;
1736 reg = <0x0 0xffbb0000 0x0 0x1000>;
1742 pinctrl-0 = <&pdm_clk0
1748 #sound-dai-cells = <0>;
1754 reg = <0x0 0xffbc0000 0x0 0x1000>;
1760 #sound-dai-cells = <0>;
1762 pinctrl-0 = <&spdifm0_pins>;
1768 reg = <0x0 0xffbd0000 0x0 0x10000>;
1799 #address-cells = <0x1>;
1800 #size-cells = <0x0>;
1808 pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
1817 snps,blen = <0 0 0 0 16 8 4>;
1833 reg = <0x0 0xffbe0000 0x0 0x10000>;
1856 #address-cells = <0x1>;
1857 #size-cells = <0x0>;
1863 snps,blen = <0 0 0 0 16 8 4>;
1879 reg = <0x0 0xffbf0000 0x0 0x10000>;
1897 reg = <0x0 0xffc00000 0x0 0x4000>;
1904 #size-cells = <0>;
1911 reg = <0x0 0xffc10000 0x0 0x4000>;
1917 fifo-depth = <0x100>;
1927 reg = <0x0 0xffc20000 0x0 0x4000>;
1933 fifo-depth = <0x100>;
1943 reg = <0x0 0xffc30000 0x0 0x4000>;
1949 fifo-depth = <0x100>;
1954 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1960 reg = <0x0 0xffc40000 0x0 0x2000>;
1974 reg = <0x0 0xffc50000 0x0 0x200>;
1985 reg = <0x0 0xffce0000 0x0 0x4000>;
1998 reg = <0x02 0x2>;
2001 reg = <0x08 0x1>;
2005 reg = <0x0a 0x10>;
2008 reg = <0x1a 0x1>;
2011 reg = <0x1b 0x1>;
2014 reg = <0x1c 0x1>;
2017 reg = <0x2d 0x1>;
2020 reg = <0x2e 0x2>;
2026 reg = <0x0 0xffd60000 0x0 0x4000>;
2027 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2044 reg = <0x0 0xffd70000 0x0 0x100>;
2051 reg = <0x0 0xffdc0000 0x0 0x10000>;
2066 reg = <0x0 0xffdf0000 0x0 0x10000>;
2069 #clock-cells = <0>;
2074 #phy-cells = <0>;
2085 #phy-cells = <0>;
2094 reg = <0x0 0xffe00000 0x0 0x10000>;
2096 #phy-cells = <0>;
2099 #clock-cells = <0>;
2106 reg = <0x0 0xffe10000 0x0 0x1000>;
2107 #sound-dai-cells = <0>;
2124 reg = <0x0 0xff610000 0x0 0x200>;
2129 gpio-ranges = <&pinctrl 0 0 32>;
2136 reg = <0x0 0xffaf0000 0x0 0x200>;
2141 gpio-ranges = <&pinctrl 0 32 32>;
2148 reg = <0x0 0xffb00000 0x0 0x200>;
2153 gpio-ranges = <&pinctrl 0 64 32>;
2160 reg = <0x0 0xffb10000 0x0 0x200>;
2165 gpio-ranges = <&pinctrl 0 96 32>;
2172 reg = <0x0 0xffb20000 0x0 0x200>;
2177 gpio-ranges = <&pinctrl 0 128 32>;