Lines Matching +full:rk3066 +full:- +full:spdif
2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3399-power.h>
13 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
41 #address-cells = <2>;
42 #size-cells = <0>;
44 cpu-map {
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
75 #cooling-cells = <2>; /* min followed by max */
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
89 compatible = "arm,cortex-a53", "arm,armv8";
91 enable-method = "psci";
97 compatible = "arm,cortex-a53", "arm,armv8";
99 enable-method = "psci";
105 compatible = "arm,cortex-a72", "arm,armv8";
107 enable-method = "psci";
108 #cooling-cells = <2>; /* min followed by max */
114 compatible = "arm,cortex-a72", "arm,armv8";
116 enable-method = "psci";
121 display_subsystem: display-subsystem {
122 compatible = "rockchip,display-subsystem";
127 route_hdmi: route-hdmi {
136 route_edp: route-edp {
148 compatible = "arm,cortex-a53-pmu";
153 compatible = "arm,cortex-a72-pmu";
158 compatible = "arm,psci-1.0";
163 compatible = "arm,armv8-timer";
168 arm,no-tick-in-suspend;
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "xin24m";
175 #clock-cells = <0>;
179 compatible = "simple-bus";
180 #address-cells = <2>;
181 #size-cells = <2>;
184 dmac_bus: dma-controller@ff6d0000 {
189 #dma-cells = <1>;
191 clock-names = "apb_pclk";
194 dmac_peri: dma-controller@ff6e0000 {
199 #dma-cells = <1>;
201 clock-names = "apb_pclk";
206 compatible = "rockchip,rk3399-crypto";
208 clock-names = "sclk_crypto0", "sclk_crypto1";
214 compatible = "rockchip,rk3399-pcie";
217 reg-names = "axi-base", "apb-base";
218 #address-cells = <3>;
219 #size-cells = <2>;
220 #interrupt-cells = <1>;
221 aspm-no-l0s;
222 bus-range = <0x0 0x1>;
225 clock-names = "aclk", "aclk-perf",
230 interrupt-names = "sys", "legacy", "client";
231 interrupt-map-mask = <0 0 0 7>;
232 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
236 linux,pci-domain = <0>;
237 max-link-speed = <1>;
238 msi-map = <0x0 &its 0x0 0x1000>;
240 phy-names = "pcie-phy";
247 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
251 pcie0_intc: interrupt-controller {
252 interrupt-controller;
253 #address-cells = <0>;
254 #interrupt-cells = <1>;
259 compatible = "rockchip,rk3399-gmac";
262 interrupt-names = "macirq";
267 clock-names = "stmmaceth", "mac_clk_rx",
271 power-domains = <&power RK3399_PD_GMAC>;
273 reset-names = "stmmaceth";
279 compatible = "rockchip,rk3399-dw-mshc",
280 "rockchip,rk3288-dw-mshc";
283 max-frequency = <150000000>;
286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
287 fifo-depth = <0x100>;
288 power-domains = <&power RK3399_PD_SDIOAUDIO>;
290 reset-names = "reset";
295 compatible = "rockchip,rk3399-dw-mshc",
296 "rockchip,rk3288-dw-mshc";
299 max-frequency = <150000000>;
302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
303 fifo-depth = <0x100>;
304 power-domains = <&power RK3399_PD_SD>;
306 reset-names = "reset";
311 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
314 arasan,soc-ctl-syscon = <&grf>;
315 assigned-clocks = <&cru SCLK_EMMC>;
316 assigned-clock-rates = <200000000>;
317 max-frequency = <150000000>;
319 clock-names = "clk_xin", "clk_ahb";
320 clock-output-names = "emmc_cardclock";
321 #clock-cells = <0>;
323 phy-names = "phy_arasan";
324 power-domains = <&power RK3399_PD_EMMC>;
329 compatible = "generic-ehci";
334 clock-names = "usbhost", "arbiter",
337 phy-names = "usb";
338 power-domains = <&power RK3399_PD_PERIHP>;
343 compatible = "generic-ohci";
348 clock-names = "usbhost", "arbiter",
351 phy-names = "usb";
352 power-domains = <&power RK3399_PD_PERIHP>;
357 compatible = "generic-ehci";
362 clock-names = "usbhost", "arbiter",
365 phy-names = "usb";
366 power-domains = <&power RK3399_PD_PERIHP>;
371 compatible = "generic-ohci";
376 clock-names = "usbhost", "arbiter",
379 phy-names = "usb";
380 power-domains = <&power RK3399_PD_PERIHP>;
385 compatible = "rockchip,rk3399-dwc3";
388 clock-names = "ref_clk", "suspend_clk",
390 power-domains = <&power RK3399_PD_USB3>;
392 reset-names = "usb3-otg";
393 #address-cells = <2>;
394 #size-cells = <2>;
404 phy-names = "usb2-phy", "usb3-phy";
407 snps,dis-u2-freeclk-exists-quirk;
409 snps,dis-del-phy-power-chg-quirk;
410 snps,tx-ipgap-linecheck-dis-quirk;
411 snps,xhci-slow-suspend-quirk;
412 snps,xhci-trb-ent-quirk;
413 snps,usb3-warm-reset-on-resume-quirk;
419 compatible = "rockchip,rk3399-dwc3";
422 clock-names = "ref_clk", "suspend_clk",
424 power-domains = <&power RK3399_PD_USB3>;
426 reset-names = "usb3-otg";
427 #address-cells = <2>;
428 #size-cells = <2>;
438 phy-names = "usb2-phy", "usb3-phy";
441 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis-del-phy-power-chg-quirk;
444 snps,tx-ipgap-linecheck-dis-quirk;
445 snps,xhci-slow-suspend-quirk;
446 snps,xhci-trb-ent-quirk;
447 snps,usb3-warm-reset-on-resume-quirk;
452 gic: interrupt-controller@fee00000 {
453 compatible = "arm,gic-v3";
454 #interrupt-cells = <4>;
455 #address-cells = <2>;
456 #size-cells = <2>;
458 interrupt-controller;
466 its: interrupt-controller@fee20000 {
467 compatible = "arm,gic-v3-its";
468 msi-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "rockchip,rk3399-saradc";
487 #io-channel-cells = <1>;
489 clock-names = "saradc", "apb_pclk";
491 reset-names = "saradc-apb";
496 compatible = "rockchip,rk3399-i2c";
498 assigned-clocks = <&cru SCLK_I2C1>;
499 assigned-clock-rates = <200000000>;
501 clock-names = "i2c", "pclk";
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c1_xfer>;
505 #address-cells = <1>;
506 #size-cells = <0>;
511 compatible = "rockchip,rk3399-i2c";
513 assigned-clocks = <&cru SCLK_I2C2>;
514 assigned-clock-rates = <200000000>;
516 clock-names = "i2c", "pclk";
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c2_xfer>;
520 #address-cells = <1>;
521 #size-cells = <0>;
526 compatible = "rockchip,rk3399-i2c";
528 assigned-clocks = <&cru SCLK_I2C3>;
529 assigned-clock-rates = <200000000>;
531 clock-names = "i2c", "pclk";
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c3_xfer>;
535 #address-cells = <1>;
536 #size-cells = <0>;
541 compatible = "rockchip,rk3399-i2c";
543 assigned-clocks = <&cru SCLK_I2C5>;
544 assigned-clock-rates = <200000000>;
546 clock-names = "i2c", "pclk";
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c5_xfer>;
550 #address-cells = <1>;
551 #size-cells = <0>;
556 compatible = "rockchip,rk3399-i2c";
558 assigned-clocks = <&cru SCLK_I2C6>;
559 assigned-clock-rates = <200000000>;
561 clock-names = "i2c", "pclk";
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2c6_xfer>;
565 #address-cells = <1>;
566 #size-cells = <0>;
571 compatible = "rockchip,rk3399-i2c";
573 assigned-clocks = <&cru SCLK_I2C7>;
574 assigned-clock-rates = <200000000>;
576 clock-names = "i2c", "pclk";
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c7_xfer>;
580 #address-cells = <1>;
581 #size-cells = <0>;
586 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
589 clock-names = "baudclk", "apb_pclk";
591 reg-shift = <2>;
592 reg-io-width = <4>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&uart0_xfer>;
599 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
602 clock-names = "baudclk", "apb_pclk";
604 reg-shift = <2>;
605 reg-io-width = <4>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&uart1_xfer>;
612 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615 clock-names = "baudclk", "apb_pclk";
617 clock-frequency = <24000000>;
618 reg-shift = <2>;
619 reg-io-width = <4>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&uart2c_xfer>;
626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
629 clock-names = "baudclk", "apb_pclk";
631 reg-shift = <2>;
632 reg-io-width = <4>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&uart3_xfer>;
639 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
642 clock-names = "spiclk", "apb_pclk";
644 pinctrl-names = "default";
645 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
646 #address-cells = <1>;
647 #size-cells = <0>;
652 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
655 clock-names = "spiclk", "apb_pclk";
657 pinctrl-names = "default";
658 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
659 #address-cells = <1>;
660 #size-cells = <0>;
665 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
668 clock-names = "spiclk", "apb_pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
672 #address-cells = <1>;
673 #size-cells = <0>;
678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
681 clock-names = "spiclk", "apb_pclk";
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
685 #address-cells = <1>;
686 #size-cells = <0>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
694 clock-names = "spiclk", "apb_pclk";
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
703 thermal_zones: thermal-zones {
705 polling-delay-passive = <100>;
706 polling-delay = <1000>;
708 thermal-sensors = <&tsadc 0>;
728 cooling-maps {
731 cooling-device =
736 cooling-device =
744 polling-delay-passive = <100>;
745 polling-delay = <1000>;
747 thermal-sensors = <&tsadc 1>;
762 cooling-maps {
765 cooling-device =
773 compatible = "rockchip,rk3399-tsadc";
776 assigned-clocks = <&cru SCLK_TSADC>;
777 assigned-clock-rates = <750000>;
779 clock-names = "tsadc", "apb_pclk";
781 reset-names = "tsadc-apb";
783 rockchip,hw-tshut-temp = <95000>;
784 pinctrl-names = "init", "default", "sleep";
785 pinctrl-0 = <&otp_gpio>;
786 pinctrl-1 = <&otp_out>;
787 pinctrl-2 = <&otp_gpio>;
788 #thermal-sensor-cells = <1>;
917 pmu: power-management@ff310000 {
918 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
928 power: power-controller {
929 compatible = "rockchip,rk3399-power-controller";
930 #power-domain-cells = <1>;
931 #address-cells = <1>;
932 #size-cells = <0>;
987 #address-cells = <1>;
988 #size-cells = <0>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1073 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1075 #address-cells = <1>;
1076 #size-cells = <1>;
1078 pmu_io_domains: io-domains {
1079 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1085 compatible = "rockchip,rk3399-pmusgrf", "syscon";
1090 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1093 clock-names = "spiclk", "apb_pclk";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1103 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1106 clock-names = "baudclk", "apb_pclk";
1108 reg-shift = <2>;
1109 reg-io-width = <4>;
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&uart4_xfer>;
1116 compatible = "rockchip,rk3399-i2c";
1118 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1119 assigned-clock-rates = <200000000>;
1121 clock-names = "i2c", "pclk";
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&i2c4_xfer>;
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1131 compatible = "rockchip,rk3399-i2c";
1133 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1134 assigned-clock-rates = <200000000>;
1136 clock-names = "i2c", "pclk";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&i2c8_xfer>;
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1146 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1148 #pwm-cells = <3>;
1149 pinctrl-names = "active";
1150 pinctrl-0 = <&pwm0_pin>;
1152 clock-names = "pwm";
1157 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1159 #pwm-cells = <3>;
1160 pinctrl-names = "active";
1161 pinctrl-0 = <&pwm1_pin>;
1163 clock-names = "pwm";
1168 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1170 #pwm-cells = <3>;
1171 pinctrl-names = "active";
1172 pinctrl-0 = <&pwm2_pin>;
1174 clock-names = "pwm";
1179 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1181 #pwm-cells = <3>;
1182 pinctrl-names = "active";
1183 pinctrl-0 = <&pwm3a_pin>;
1185 clock-names = "pwm";
1190 compatible = "rockchip,rk3399-cic", "syscon";
1196 compatible = "rockchip,rk3399-dfi";
1199 clock-names = "pclk_ddr_mon";
1204 compatible = "rockchip,rk3399-dmc";
1205 devfreq-events = <&dfi>;
1208 clock-names = "dmc_clk";
1220 compatible = "rockchip,rk3399-efuse";
1222 #address-cells = <1>;
1223 #size-cells = <1>;
1225 clock-names = "pclk_efuse";
1228 cpu_id: cpu-id@7 {
1231 cpub_leakage: cpu-leakage@17 {
1234 gpu_leakage: gpu-leakage@18 {
1237 center_leakage: center-leakage@19 {
1240 cpul_leakage: cpu-leakage@1a {
1243 logic_leakage: logic-leakage@1b {
1246 wafer_info: wafer-info@1c {
1251 pmucru: pmu-clock-controller@ff750000 {
1252 compatible = "rockchip,rk3399-pmucru";
1255 #clock-cells = <1>;
1256 #reset-cells = <1>;
1257 assigned-clocks = <&pmucru PLL_PPLL>;
1258 assigned-clock-rates = <676000000>;
1261 cru: clock-controller@ff760000 {
1262 compatible = "rockchip,rk3399-cru";
1265 #clock-cells = <1>;
1266 #reset-cells = <1>;
1267 assigned-clocks =
1275 assigned-clock-rates =
1286 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1288 #address-cells = <1>;
1289 #size-cells = <1>;
1291 io_domains: io-domains {
1292 compatible = "rockchip,rk3399-io-voltage-domain";
1296 u2phy0: usb2-phy@e450 {
1297 compatible = "rockchip,rk3399-usb2phy";
1300 clock-names = "phyclk";
1301 #clock-cells = <0>;
1302 clock-output-names = "clk_usbphy0_480m";
1305 u2phy0_host: host-port {
1306 #phy-cells = <0>;
1308 interrupt-names = "linestate";
1312 u2phy0_otg: otg-port {
1313 #phy-cells = <0>;
1317 interrupt-names = "otg-bvalid", "otg-id",
1323 u2phy1: usb2-phy@e460 {
1324 compatible = "rockchip,rk3399-usb2phy";
1327 clock-names = "phyclk";
1328 #clock-cells = <0>;
1329 clock-output-names = "clk_usbphy1_480m";
1332 u2phy1_host: host-port {
1333 #phy-cells = <0>;
1335 interrupt-names = "linestate";
1339 u2phy1_otg: otg-port {
1340 #phy-cells = <0>;
1344 interrupt-names = "otg-bvalid", "otg-id",
1351 compatible = "rockchip,rk3399-emmc-phy";
1354 clock-names = "emmcclk";
1355 #phy-cells = <0>;
1359 pcie_phy: pcie-phy {
1360 compatible = "rockchip,rk3399-pcie-phy";
1362 clock-names = "refclk";
1363 #phy-cells = <0>;
1365 reset-names = "phy";
1371 compatible = "rockchip,rk3399-typec-phy";
1373 #phy-cells = <1>;
1376 clock-names = "tcpdcore", "tcpdphy-ref";
1377 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1378 assigned-clock-rates = <50000000>;
1379 power-domains = <&power RK3399_PD_TCPD0>;
1383 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1385 rockchip,typec-conn-dir = <0xe580 0 16>;
1386 rockchip,usb3tousb2-en = <0xe580 3 19>;
1387 rockchip,usb3-host-disable = <0x2434 0 16>;
1388 rockchip,usb3-host-port = <0x2434 12 28>;
1389 rockchip,external-psm = <0xe588 14 30>;
1390 rockchip,pipe-status = <0xe5c0 0 0>;
1391 rockchip,uphy-dp-sel = <0x6268 19 19>;
1394 tcphy0_dp: dp-port {
1395 #phy-cells = <0>;
1398 tcphy0_usb3: usb3-port {
1399 #phy-cells = <0>;
1404 compatible = "rockchip,rk3399-typec-phy";
1406 #phy-cells = <1>;
1409 clock-names = "tcpdcore", "tcpdphy-ref";
1410 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1411 assigned-clock-rates = <50000000>;
1412 power-domains = <&power RK3399_PD_TCPD1>;
1416 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1418 rockchip,typec-conn-dir = <0xe58c 0 16>;
1419 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1420 rockchip,usb3-host-disable = <0x2444 0 16>;
1421 rockchip,usb3-host-port = <0x2444 12 28>;
1422 rockchip,external-psm = <0xe594 14 30>;
1423 rockchip,pipe-status = <0xe5c0 16 16>;
1424 rockchip,uphy-dp-sel = <0x6268 3 19>;
1427 tcphy1_dp: dp-port {
1428 #phy-cells = <0>;
1431 tcphy1_usb3: usb3-port {
1432 #phy-cells = <0>;
1437 compatible = "snps,dw-wdt";
1444 compatible = "rockchip,rk3399-timer";
1448 clock-names = "pclk", "timer";
1451 spdif: spdif@ff870000 { label
1452 compatible = "rockchip,rk3399-spdif";
1456 dma-names = "tx";
1457 clock-names = "mclk", "hclk";
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&spdif_bus>;
1461 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1466 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1471 dma-names = "tx", "rx";
1472 clock-names = "i2s_clk", "i2s_hclk";
1474 pinctrl-names = "default";
1475 pinctrl-0 = <&i2s0_8ch_bus>;
1476 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1481 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1485 dma-names = "tx", "rx";
1486 clock-names = "i2s_clk", "i2s_hclk";
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&i2s1_2ch_bus>;
1490 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1495 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1499 dma-names = "tx", "rx";
1500 clock-names = "i2s_clk", "i2s_hclk";
1502 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1507 compatible = "rockchip,rk3399-i2c";
1509 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1510 assigned-clock-rates = <200000000>;
1512 clock-names = "i2c", "pclk";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&i2c0_xfer>;
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1522 compatible = "rockchip,rk3399-vop-lit";
1526 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1528 reset-names = "axi", "ahb", "dclk";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1535 remote-endpoint = <&mipi_in_vopl>;
1540 remote-endpoint = <&hdmi_in_vopl>;
1545 remote-endpoint = <&edp_in_vopl>;
1551 compatible = "rockchip,rk3399-vop-big";
1555 #clock-cells = <0>;
1556 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1558 reset-names = "axi", "ahb", "dclk";
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1565 remote-endpoint = <&mipi_in_vopb>;
1570 remote-endpoint = <&hdmi_in_vopb>;
1575 remote-endpoint = <&edp_in_vopb>;
1581 compatible = "rockchip,rk3399-dw-hdmi";
1583 reg-io-width = <4>;
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&hdmi_i2c_xfer>;
1587 power-domains = <&power RK3399_PD_HDCP>;
1590 clock-names = "iahb", "isfr", "vpll", "grf";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1599 remote-endpoint = <&vopb_out_hdmi>;
1603 remote-endpoint = <&vopl_out_hdmi>;
1615 clock-names = "ref", "pclk", "phy_cfg";
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1629 remote-endpoint = <&vopb_out_mipi>;
1633 remote-endpoint = <&vopl_out_mipi>;
1640 compatible = "rockchip,rk3399-edp";
1644 clock-names = "dp", "pclk";
1645 power-domains = <&power RK3399_PD_EDP>;
1647 reset-names = "dp";
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&edp_hpd>;
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1664 remote-endpoint = <&vopb_out_edp>;
1669 remote-endpoint = <&vopl_out_edp>;
1676 compatible = "rockchip,rk3399-pinctrl";
1679 #address-cells = <2>;
1680 #size-cells = <2>;
1684 compatible = "rockchip,gpio-bank";
1689 gpio-controller;
1690 #gpio-cells = <0x2>;
1692 interrupt-controller;
1693 #interrupt-cells = <0x2>;
1697 compatible = "rockchip,gpio-bank";
1702 gpio-controller;
1703 #gpio-cells = <0x2>;
1705 interrupt-controller;
1706 #interrupt-cells = <0x2>;
1710 compatible = "rockchip,gpio-bank";
1715 gpio-controller;
1716 #gpio-cells = <0x2>;
1718 interrupt-controller;
1719 #interrupt-cells = <0x2>;
1723 compatible = "rockchip,gpio-bank";
1728 gpio-controller;
1729 #gpio-cells = <0x2>;
1731 interrupt-controller;
1732 #interrupt-cells = <0x2>;
1736 compatible = "rockchip,gpio-bank";
1741 gpio-controller;
1742 #gpio-cells = <0x2>;
1744 interrupt-controller;
1745 #interrupt-cells = <0x2>;
1748 pcfg_pull_up: pcfg-pull-up {
1749 bias-pull-up;
1752 pcfg_pull_down: pcfg-pull-down {
1753 bias-pull-down;
1756 pcfg_pull_none: pcfg-pull-none {
1757 bias-disable;
1760 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1761 bias-disable;
1762 drive-strength = <12>;
1765 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1766 bias-pull-up;
1767 drive-strength = <8>;
1770 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1771 bias-pull-down;
1772 drive-strength = <4>;
1775 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1776 bias-pull-up;
1777 drive-strength = <2>;
1780 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1781 bias-pull-down;
1782 drive-strength = <12>;
1785 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1786 bias-disable;
1787 drive-strength = <13>;
1791 clk_32k: clk-32k {
1797 edp_hpd: edp-hpd {
1804 rgmii_pins: rgmii-pins {
1838 rmii_pins: rmii-pins {
1864 i2c0_xfer: i2c0-xfer {
1872 i2c1_xfer: i2c1-xfer {
1880 i2c2_xfer: i2c2-xfer {
1888 i2c3_xfer: i2c3-xfer {
1896 i2c4_xfer: i2c4-xfer {
1904 i2c5_xfer: i2c5-xfer {
1912 i2c6_xfer: i2c6-xfer {
1920 i2c7_xfer: i2c7-xfer {
1928 i2c8_xfer: i2c8-xfer {
1936 i2s0_8ch_bus: i2s0-8ch-bus {
1951 i2s1_2ch_bus: i2s1-2ch-bus {
1962 sdio0_bus1: sdio0-bus1 {
1967 sdio0_bus4: sdio0-bus4 {
1975 sdio0_cmd: sdio0-cmd {
1980 sdio0_clk: sdio0-clk {
1985 sdio0_cd: sdio0-cd {
1990 sdio0_pwr: sdio0-pwr {
1995 sdio0_bkpwr: sdio0-bkpwr {
2000 sdio0_wp: sdio0-wp {
2005 sdio0_int: sdio0-int {
2012 sdmmc_bus1: sdmmc-bus1 {
2017 sdmmc_bus4: sdmmc-bus4 {
2025 sdmmc_clk: sdmmc-clk {
2030 sdmmc_cmd: sdmmc-cmd {
2035 sdmmc_cd: sdmcc-cd {
2040 sdmmc_wp: sdmmc-wp {
2047 ap_pwroff: ap-pwroff {
2051 ddrio_pwroff: ddrio-pwroff {
2056 spdif {
2057 spdif_bus: spdif-bus {
2062 spdif_bus_1: spdif-bus-1 {
2069 spi0_clk: spi0-clk {
2073 spi0_cs0: spi0-cs0 {
2077 spi0_cs1: spi0-cs1 {
2081 spi0_tx: spi0-tx {
2085 spi0_rx: spi0-rx {
2092 spi1_clk: spi1-clk {
2096 spi1_cs0: spi1-cs0 {
2100 spi1_rx: spi1-rx {
2104 spi1_tx: spi1-tx {
2111 spi2_clk: spi2-clk {
2115 spi2_cs0: spi2-cs0 {
2119 spi2_rx: spi2-rx {
2123 spi2_tx: spi2-tx {
2130 spi3_clk: spi3-clk {
2134 spi3_cs0: spi3-cs0 {
2138 spi3_rx: spi3-rx {
2142 spi3_tx: spi3-tx {
2149 spi4_clk: spi4-clk {
2153 spi4_cs0: spi4-cs0 {
2157 spi4_rx: spi4-rx {
2161 spi4_tx: spi4-tx {
2168 spi5_clk: spi5-clk {
2172 spi5_cs0: spi5-cs0 {
2176 spi5_rx: spi5-rx {
2180 spi5_tx: spi5-tx {
2187 otp_gpio: otp-gpio {
2191 otp_out: otp-out {
2197 uart0_xfer: uart0-xfer {
2203 uart0_cts: uart0-cts {
2208 uart0_rts: uart0-rts {
2215 uart1_xfer: uart1-xfer {
2223 uart2a_xfer: uart2a-xfer {
2231 uart2b_xfer: uart2b-xfer {
2239 uart2c_xfer: uart2c-xfer {
2247 uart3_xfer: uart3-xfer {
2253 uart3_cts: uart3-cts {
2258 uart3_rts: uart3-rts {
2265 uart4_xfer: uart4-xfer {
2273 uarthdcp_xfer: uarthdcp-xfer {
2281 pwm0_pin: pwm0-pin {
2286 vop0_pwm_pin: vop0-pwm-pin {
2293 pwm1_pin: pwm1-pin {
2298 vop1_pwm_pin: vop1-pwm-pin {
2305 pwm2_pin: pwm2-pin {
2312 pwm3a_pin: pwm3a-pin {
2319 pwm3b_pin: pwm3b-pin {
2326 hdmi_i2c_xfer: hdmi-i2c-xfer {
2332 hdmi_cec: hdmi-cec {
2339 pcie_clkreqn: pci-clkreqn {
2344 pcie_clkreqnb: pci-clkreqnb {
2349 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2354 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {