arm/dts/rk3308-u-boot.dtsi

4  * SPDX-License-Identifier:     GPL-2.0+
14 		stdout-path = &uart2;
15 		u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
18 	secure-otp@ff2a8000 {
19 		compatible = "rockchip,rk3308-secure-otp";
23 		u-boot,dm-pre-reloc;
28 	u-boot,dm-pre-reloc;
33 	u-boot,dm-pre-reloc;
37 	u-boot,dm-pre-reloc;
41 	u-boot,dm-pre-reloc;
45 	u-boot,dm-pre-reloc;
49 	u-boot,dm-pre-reloc;
51 	#address-cells = <1>;
52 	#size-cells = <0>;
54 	nand@0 {
55 		u-boot,dm-spl;
57 		nand-ecc-mode = "hw";
58 		nand-ecc-strength = <16>;
59 		nand-ecc-step-size = <1024>;
64 	u-boot,dm-pre-reloc;
68 	u-boot,dm-spl;
72 	u-boot,dm-spl;
76 	u-boot,dm-pre-reloc;
80 	u-boot,dm-spl;
84 	u-boot,dm-spl;
88 	u-boot,dm-spl;
92 	u-boot,dm-spl;
96 	u-boot,dm-spl;
100 	u-boot,dm-pre-reloc;
103 	#address-cells = <1>;
104 	#size-cells = <0>;
106 		u-boot,dm-spl;
107 		compatible = "spi-nand";
109 		spi-tx-bus-width = <1>;
110 		spi-rx-bus-width = <4>;
111 		spi-max-frequency = <96000000>;
114 		u-boot,dm-spl;
115 		compatible = "jedec,spi-nor";
118 		spi-tx-bus-width = <1>;
119 		spi-rx-bus-width = <4>;
120 		spi-max-frequency = <96000000>;
125 	u-boot,dm-pre-reloc;
130 	u-boot,dm-pre-reloc;
135 	u-boot,dm-pre-reloc;
139 	u-boot,dm-pre-reloc;
143 	u-boot,dm-pre-reloc;
144 	clock-frequency = <24000000>;
149 	u-boot,dm-pre-reloc;
153 	u-boot,dm-pre-reloc;
157 	u-boot,dm-pre-reloc;
161 	u-boot,dm-pre-reloc;
166 	u-boot,dm-pre-reloc;
171 	u-boot,dm-pre-reloc;