Lines Matching +full:usb +full:- +full:grf
2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
56 enable-method = "rockchip,rk3066-smp";
61 compatible = "arm,cortex-a12";
63 operating-points = <
79 #cooling-cells = <2>; /* min followed by max */
80 clock-latency = <40000>;
86 compatible = "arm,cortex-a12";
92 compatible = "arm,cortex-a12";
98 compatible = "arm,cortex-a12";
105 compatible = "arm,amba-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
110 dmac_peri: dma-controller@ff250000 {
112 broken-no-flushp;
116 #dma-cells = <1>;
118 clock-names = "apb_pclk";
121 dmac_bus_ns: dma-controller@ff600000 {
123 broken-no-flushp;
127 #dma-cells = <1>;
129 clock-names = "apb_pclk";
133 dmac_bus_s: dma-controller@ffb20000 {
135 broken-no-flushp;
139 #dma-cells = <1>;
141 clock-names = "apb_pclk";
146 compatible = "fixed-clock";
147 clock-frequency = <24000000>;
148 clock-output-names = "xin24m";
149 #clock-cells = <0>;
153 compatible = "arm,psci-1.0";
158 arm,use-physical-timer;
159 compatible = "arm,armv7-timer";
164 clock-frequency = <24000000>;
165 always-on;
168 display_subsystem: display-subsystem {
169 compatible = "rockchip,display-subsystem";
174 route_hdmi: route-hdmi {
183 route_edp: route-edp {
192 route_dsi0: route-dsi0 {
201 route_lvds: route-lvds {
213 compatible = "rockchip,rk3288-dw-mshc";
214 max-frequency = <150000000>;
217 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
218 fifo-depth = <0x100>;
219 cd-gpios = <&gpio6 RK_PC6 GPIO_ACTIVE_HIGH>;
226 compatible = "rockchip,rk3288-dw-mshc";
227 max-frequency = <150000000>;
230 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
231 fifo-depth = <0x100>;
238 compatible = "rockchip,rk3288-dw-mshc";
239 max-frequency = <150000000>;
242 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
243 fifo-depth = <0x100>;
250 compatible = "rockchip,rk3288-dw-mshc";
251 max-frequency = <150000000>;
254 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
255 fifo-depth = <0x100>;
265 #io-channel-cells = <1>;
267 clock-names = "saradc", "apb_pclk";
272 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
274 clock-names = "spiclk", "apb_pclk";
276 dma-names = "tx", "rx";
278 pinctrl-names = "default";
279 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
281 #address-cells = <1>;
282 #size-cells = <0>;
287 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
289 clock-names = "spiclk", "apb_pclk";
291 dma-names = "tx", "rx";
293 pinctrl-names = "default";
294 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
296 #address-cells = <1>;
297 #size-cells = <0>;
302 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
304 clock-names = "spiclk", "apb_pclk";
306 dma-names = "tx", "rx";
308 pinctrl-names = "default";
309 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
311 #address-cells = <1>;
312 #size-cells = <0>;
317 compatible = "rockchip,rk3288-i2c";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 clock-names = "i2c";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c1_xfer>;
330 compatible = "rockchip,rk3288-i2c";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 clock-names = "i2c";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c3_xfer>;
343 compatible = "rockchip,rk3288-i2c";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 clock-names = "i2c";
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c4_xfer>;
356 compatible = "rockchip,rk3288-i2c";
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clock-names = "i2c";
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c5_xfer>;
369 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
372 reg-shift = <2>;
373 reg-io-width = <4>;
374 clock-frequency = <24000000>;
376 clock-names = "baudclk", "apb_pclk";
377 pinctrl-names = "default";
378 pinctrl-0 = <&uart0_xfer>;
383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
386 reg-shift = <2>;
387 reg-io-width = <4>;
388 clock-frequency = <24000000>;
390 clock-names = "baudclk", "apb_pclk";
391 pinctrl-names = "default";
392 pinctrl-0 = <&uart1_xfer>;
397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
400 reg-shift = <2>;
401 reg-io-width = <4>;
402 clock-frequency = <24000000>;
404 clock-names = "baudclk", "apb_pclk";
405 pinctrl-names = "default";
406 pinctrl-0 = <&uart2_xfer>;
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clock-frequency = <24000000>;
417 clock-names = "baudclk", "apb_pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart3_xfer>;
424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
427 reg-shift = <2>;
428 reg-io-width = <4>;
429 clock-frequency = <24000000>;
431 clock-names = "baudclk", "apb_pclk";
432 pinctrl-names = "default";
433 pinctrl-0 = <&uart4_xfer>;
437 thermal: thermal-zones {
438 #include "rk3288-thermal.dtsi"
442 compatible = "rockchip,rk3288-tsadc";
446 clock-names = "tsadc", "apb_pclk";
448 reset-names = "tsadc-apb";
449 pinctrl-names = "otp_out";
450 pinctrl-0 = <&otp_out>;
451 #thermal-sensor-cells = <1>;
452 hw-shut-temp = <125000>;
457 compatible = "rockchip,rk3288-gmac";
460 interrupt-names = "macirq";
461 rockchip,grf = <&grf>;
466 clock-names = "stmmaceth",
472 usb_host0_ehci: usb@ff500000 {
473 compatible = "generic-ehci";
477 clock-names = "usbhost";
479 phy-names = "usb";
485 usb_host1: usb@ff540000 {
486 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
491 clock-names = "otg";
493 phy-names = "usb2-phy";
497 usb_otg: usb@ff580000 {
498 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
503 clock-names = "otg";
506 phy-names = "usb2-phy";
510 usb_hsic: usb@ff5c0000 {
511 compatible = "generic-ehci";
515 clock-names = "usbhost";
520 compatible = "rockchip,rk3288-dmc", "syscon";
522 rockchip,grf = <&grf>;
534 clock-names = "pclk_ddrupctl0", "pclk_publ0",
540 compatible = "rockchip,rk3288-i2c";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 clock-names = "i2c";
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c0_xfer>;
553 compatible = "rockchip,rk3288-i2c";
556 #address-cells = <1>;
557 #size-cells = <0>;
558 clock-names = "i2c";
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c2_xfer>;
566 compatible = "rockchip,rk3288-pwm";
568 #pwm-cells = <3>;
569 pinctrl-names = "active";
570 pinctrl-0 = <&pwm0_pin>;
572 clock-names = "pwm";
573 rockchip,grf = <&grf>;
578 compatible = "rockchip,rk3288-pwm";
580 #pwm-cells = <3>;
581 pinctrl-names = "active";
582 pinctrl-0 = <&pwm1_pin>;
584 clock-names = "pwm";
585 rockchip,grf = <&grf>;
590 compatible = "rockchip,rk3288-pwm";
592 #pwm-cells = <3>;
593 pinctrl-names = "active";
594 pinctrl-0 = <&pwm2_pin>;
596 clock-names = "pwm";
597 rockchip,grf = <&grf>;
602 compatible = "rockchip,rk3288-pwm";
604 #pwm-cells = <2>;
605 pinctrl-names = "active";
606 pinctrl-0 = <&pwm3_pin>;
608 clock-names = "pwm";
609 rockchip,grf = <&grf>;
614 compatible = "mmio-sram";
616 #address-cells = <1>;
617 #size-cells = <1>;
619 smp-sram@0 {
620 compatible = "rockchip,rk3066-smp-sram";
623 ddr_sram: ddr-sram@1000 {
624 compatible = "rockchip,rk3288-ddr-sram";
630 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
634 pmu: power-management@ff730000 {
635 compatible = "rockchip,rk3288-pmu", "syscon";
640 compatible = "rockchip,rk3288-sgrf", "syscon";
644 cru: clock-controller@ff760000 {
645 compatible = "rockchip,rk3288-cru";
647 rockchip,grf = <&grf>;
648 #clock-cells = <1>;
649 #reset-cells = <1>;
650 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
655 assigned-clock-rates = <594000000>, <400000000>,
662 grf: syscon@ff770000 { label
663 compatible = "rockchip,rk3288-grf", "syscon";
668 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
676 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
678 #sound-dai-cells = <0>;
679 clock-names = "hclk", "mclk";
682 dma-names = "tx";
684 pinctrl-names = "default";
685 pinctrl-0 = <&spdif_tx>;
686 rockchip,grf = <&grf>;
691 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
694 #address-cells = <1>;
695 #size-cells = <0>;
697 dma-names = "tx", "rx";
698 clock-names = "i2s_hclk", "i2s_clk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2s0_bus>;
706 compatible = "rockchip,rk3288-crypto";
708 clock-names = "sclk_crypto";
711 reset-names = "reset";
716 compatible = "rockchip,rk3288-vop-big";
720 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
722 reset-names = "axi", "ahb", "dclk";
724 power-domains = <&power RK3288_PD_VIO>;
727 #address-cells = <1>;
728 #size-cells = <0>;
731 remote-endpoint = <&edp_in_vopb>;
735 remote-endpoint = <&hdmi_in_vopb>;
739 remote-endpoint = <&lvds_in_vopb>;
743 remote-endpoint = <&dsi0_in_vopb>;
753 interrupt-names = "vopb_mmu";
754 power-domains = <&power RK3288_PD_VIO>;
755 #iommu-cells = <0>;
760 compatible = "rockchip,rk3288-vop-lit";
764 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
766 reset-names = "axi", "ahb", "dclk";
768 power-domains = <&power RK3288_PD_VIO>;
771 #address-cells = <1>;
772 #size-cells = <0>;
775 remote-endpoint = <&edp_in_vopl>;
779 remote-endpoint = <&hdmi_in_vopl>;
783 remote-endpoint = <&lvds_in_vopl>;
787 remote-endpoint = <&dsi0_in_vopl>;
797 interrupt-names = "vopl_mmu";
798 power-domains = <&power RK3288_PD_VIO>;
799 #iommu-cells = <0>;
804 compatible = "rockchip,rk3288-dp";
808 rockchip,grf = <&grf>;
809 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
811 reset-names = "edp";
812 power-domains = <&power RK3288_PD_VIO>;
815 #address-cells = <1>;
816 #size-cells = <0>;
819 #address-cells = <1>;
820 #size-cells = <0>;
823 remote-endpoint = <&vopb_out_edp>;
827 remote-endpoint = <&vopl_out_edp>;
834 compatible = "rockchip,rk3288-dw-hdmi";
836 reg-io-width = <4>;
837 rockchip,grf = <&grf>;
840 clock-names = "iahb", "isfr";
841 pinctrl-names = "default";
842 pinctrl-0 = <&hdmi_ddc>;
846 #address-cells = <1>;
847 #size-cells = <0>;
850 remote-endpoint = <&vopb_out_hdmi>;
854 remote-endpoint = <&vopl_out_hdmi>;
861 compatible = "rockchip,rk3288-lvds";
864 clock-names = "pclk_lvds";
865 pinctrl-names = "default";
866 pinctrl-0 = <&lcdc0_ctl>;
867 rockchip,grf = <&grf>;
870 #address-cells = <1>;
871 #size-cells = <0>;
874 #address-cells = <1>;
875 #size-cells = <0>;
878 remote-endpoint = <&vopb_out_lvds>;
882 remote-endpoint = <&vopl_out_lvds>;
889 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
893 clock-names = "ref", "pclk";
895 reset-names = "apb";
896 power-domains = <&power RK3288_PD_VIO>;
897 rockchip,grf = <&grf>;
898 #address-cells = <1>;
899 #size-cells = <0>;
902 #address-cells = <1>;
903 #size-cells = <0>;
906 #address-cells = <1>;
907 #size-cells = <0>;
910 remote-endpoint = <&vopb_out_dsi0>;
914 remote-endpoint = <&vopl_out_dsi0>;
921 compatible = "rockchip,rk3288-hdmi-audio";
922 i2s-controller = <&i2s>;
926 vpu: video-codec@ff9a0000 {
927 compatible = "rockchip,rk3288-vpu";
931 interrupt-names = "vepu", "vdpu";
933 clock-names = "aclk_vcodec", "hclk_vcodec";
934 power-domains = <&power RK3288_PD_VIDEO>;
942 interrupt-names = "vpu_mmu";
943 power-domains = <&power RK3288_PD_VIDEO>;
944 #iommu-cells = <0>;
951 "arm,mali-midgard";
956 interrupt-names = "JOB", "MMU", "GPU";
958 clock-names = "aclk_gpu";
959 operating-points = <
965 /* 500000 1200000 - See crosbug.com/p/33857 */
968 power-domains = <&power RK3288_PD_GPU>;
973 compatible = "rockchip,rk3288-noc", "syscon";
978 compatible = "rockchip,rk3288-efuse";
983 gic: interrupt-controller@ffc01000 {
984 compatible = "arm,gic-400";
985 interrupt-controller;
986 #interrupt-cells = <3>;
987 #address-cells = <0>;
997 compatible = "rockchip,rk3288-cpuidle";
1001 compatible = "rockchip,rk3288-usb-phy";
1002 rockchip,grf = <&grf>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1007 usbphy0: usb-phy0 {
1008 #phy-cells = <0>;
1011 clock-names = "phyclk";
1014 usbphy1: usb-phy1 {
1015 #phy-cells = <0>;
1018 clock-names = "phyclk";
1021 usbphy2: usb-phy2 {
1022 #phy-cells = <0>;
1025 clock-names = "phyclk";
1030 compatible = "rockchip,rk3288-pinctrl";
1031 rockchip,grf = <&grf>;
1033 #address-cells = <1>;
1034 #size-cells = <1>;
1038 compatible = "rockchip,gpio-bank";
1043 gpio-controller;
1044 #gpio-cells = <2>;
1046 interrupt-controller;
1047 #interrupt-cells = <2>;
1051 compatible = "rockchip,gpio-bank";
1056 gpio-controller;
1057 #gpio-cells = <2>;
1059 interrupt-controller;
1060 #interrupt-cells = <2>;
1064 compatible = "rockchip,gpio-bank";
1069 gpio-controller;
1070 #gpio-cells = <2>;
1072 interrupt-controller;
1073 #interrupt-cells = <2>;
1077 compatible = "rockchip,gpio-bank";
1082 gpio-controller;
1083 #gpio-cells = <2>;
1085 interrupt-controller;
1086 #interrupt-cells = <2>;
1090 compatible = "rockchip,gpio-bank";
1095 gpio-controller;
1096 #gpio-cells = <2>;
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1103 compatible = "rockchip,gpio-bank";
1108 gpio-controller;
1109 #gpio-cells = <2>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1116 compatible = "rockchip,gpio-bank";
1121 gpio-controller;
1122 #gpio-cells = <2>;
1124 interrupt-controller;
1125 #interrupt-cells = <2>;
1129 compatible = "rockchip,gpio-bank";
1134 gpio-controller;
1135 #gpio-cells = <2>;
1137 interrupt-controller;
1138 #interrupt-cells = <2>;
1142 compatible = "rockchip,gpio-bank";
1147 gpio-controller;
1148 #gpio-cells = <2>;
1150 interrupt-controller;
1151 #interrupt-cells = <2>;
1155 hdmi_ddc: hdmi-ddc {
1161 pcfg_pull_up: pcfg-pull-up {
1162 bias-pull-up;
1165 pcfg_pull_down: pcfg-pull-down {
1166 bias-pull-down;
1169 pcfg_pull_none: pcfg-pull-none {
1170 bias-disable;
1173 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1174 bias-disable;
1175 drive-strength = <12>;
1179 global_pwroff: global-pwroff {
1183 ddrio_pwroff: ddrio-pwroff {
1187 ddr0_retention: ddr0-retention {
1191 ddr1_retention: ddr1-retention {
1197 i2c0_xfer: i2c0-xfer {
1204 i2c1_xfer: i2c1-xfer {
1211 i2c2_xfer: i2c2-xfer {
1218 i2c3_xfer: i2c3-xfer {
1225 i2c4_xfer: i2c4-xfer {
1232 i2c5_xfer: i2c5-xfer {
1239 i2s0_bus: i2s0-bus {
1250 lcdc0_ctl: lcdc0-ctl {
1259 sdmmc_clk: sdmmc-clk {
1263 sdmmc_cmd: sdmmc-cmd {
1267 sdmmc_cd: sdmcc-cd {
1271 sdmmc_bus1: sdmmc-bus1 {
1275 sdmmc_bus4: sdmmc-bus4 {
1284 sdio0_bus1: sdio0-bus1 {
1288 sdio0_bus4: sdio0-bus4 {
1295 sdio0_cmd: sdio0-cmd {
1299 sdio0_clk: sdio0-clk {
1303 sdio0_cd: sdio0-cd {
1307 sdio0_wp: sdio0-wp {
1311 sdio0_pwr: sdio0-pwr {
1315 sdio0_bkpwr: sdio0-bkpwr {
1319 sdio0_int: sdio0-int {
1325 sdio1_bus1: sdio1-bus1 {
1329 sdio1_bus4: sdio1-bus4 {
1336 sdio1_cd: sdio1-cd {
1340 sdio1_wp: sdio1-wp {
1344 sdio1_bkpwr: sdio1-bkpwr {
1348 sdio1_int: sdio1-int {
1352 sdio1_cmd: sdio1-cmd {
1356 sdio1_clk: sdio1-clk {
1360 sdio1_pwr: sdio1-pwr {
1366 emmc_clk: emmc-clk {
1370 emmc_cmd: emmc-cmd {
1374 emmc_pwr: emmc-pwr {
1378 emmc_bus1: emmc-bus1 {
1382 emmc_bus4: emmc-bus4 {
1389 emmc_bus8: emmc-bus8 {
1402 spi0_clk: spi0-clk {
1405 spi0_cs0: spi0-cs0 {
1408 spi0_tx: spi0-tx {
1411 spi0_rx: spi0-rx {
1414 spi0_cs1: spi0-cs1 {
1419 spi1_clk: spi1-clk {
1422 spi1_cs0: spi1-cs0 {
1425 spi1_rx: spi1-rx {
1428 spi1_tx: spi1-tx {
1434 spi2_cs1: spi2-cs1 {
1437 spi2_clk: spi2-clk {
1440 spi2_cs0: spi2-cs0 {
1443 spi2_rx: spi2-rx {
1446 spi2_tx: spi2-tx {
1452 uart0_xfer: uart0-xfer {
1457 uart0_cts: uart0-cts {
1461 uart0_rts: uart0-rts {
1467 uart1_xfer: uart1-xfer {
1472 uart1_cts: uart1-cts {
1476 uart1_rts: uart1-rts {
1482 uart2_xfer: uart2-xfer {
1490 uart3_xfer: uart3-xfer {
1495 uart3_cts: uart3-cts {
1499 uart3_rts: uart3-rts {
1505 uart4_xfer: uart4-xfer {
1510 uart4_cts: uart4-cts {
1514 uart4_rts: uart4-rts {
1520 otp_out: otp-out {
1526 pwm0_pin: pwm0-pin {
1532 pwm1_pin: pwm1-pin {
1538 pwm2_pin: pwm2-pin {
1544 pwm3_pin: pwm3-pin {
1550 rgmii_pins: rgmii-pins {
1568 rmii_pins: rmii-pins {
1583 spdif_tx: spdif-tx {
1589 power: power-controller {
1590 compatible = "rockchip,rk3288-power-controller";
1591 #power-domain-cells = <1>;
1593 #address-cells = <1>;
1594 #size-cells = <0>;