Lines Matching full:cru
9 #include <dt-bindings/clock/rk3288-cru.h>
81 clocks = <&cru ARMCLK>;
82 resets = <&cru SRST_CORE0>;
88 resets = <&cru SRST_CORE1>;
94 resets = <&cru SRST_CORE2>;
100 resets = <&cru SRST_CORE3>;
117 clocks = <&cru ACLK_DMAC2>;
128 clocks = <&cru ACLK_DMAC1>;
140 clocks = <&cru ACLK_DMAC1>;
215 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
216 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
228 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
229 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
240 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
241 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
252 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
253 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
266 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
288 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
303 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
323 clocks = <&cru PCLK_I2C1>;
336 clocks = <&cru PCLK_I2C3>;
349 clocks = <&cru PCLK_I2C4>;
362 clocks = <&cru PCLK_I2C5>;
375 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
416 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
430 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
445 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
447 resets = <&cru SRST_TSADC>;
462 clocks = <&cru SCLK_MAC>,
463 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
464 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
465 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
476 clocks = <&cru HCLK_USBHOST0>;
490 clocks = <&cru HCLK_USBHOST1>;
502 clocks = <&cru HCLK_OTG0>;
514 clocks = <&cru HCLK_HSIC>;
521 rockchip,cru = <&cru>;
531 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
532 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
533 <&cru ARMCLK>;
546 clocks = <&cru PCLK_I2C0>;
559 clocks = <&cru PCLK_I2C2>;
571 clocks = <&cru PCLK_PWM>;
583 clocks = <&cru PCLK_PWM>;
595 clocks = <&cru PCLK_PWM>;
607 clocks = <&cru PCLK_PWM>;
644 cru: clock-controller@ff760000 { label
645 compatible = "rockchip,rk3288-cru";
650 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
651 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
652 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
653 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
654 <&cru PCLK_PERI>;
670 clocks = <&cru PCLK_WDT>;
680 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
699 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
709 clocks = <&cru SCLK_CRYPTO>;
710 resets = <&cru SRST_CRYPTO>;
719 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
721 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
763 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
765 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
807 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
810 resets = <&cru 111>;
839 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
863 clocks = <&cru PCLK_LVDS_PHY>;
892 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
894 resets = <&cru SRST_MIPIDSI0>;
932 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
957 clocks = <&cru ACLK_GPU>;
1010 clocks = <&cru SCLK_OTGPHY0>;
1017 clocks = <&cru SCLK_OTGPHY1>;
1024 clocks = <&cru SCLK_OTGPHY2>;
1041 clocks = <&cru PCLK_GPIO0>;
1054 clocks = <&cru PCLK_GPIO1>;
1067 clocks = <&cru PCLK_GPIO2>;
1080 clocks = <&cru PCLK_GPIO3>;
1093 clocks = <&cru PCLK_GPIO4>;
1106 clocks = <&cru PCLK_GPIO5>;
1119 clocks = <&cru PCLK_GPIO6>;
1132 clocks = <&cru PCLK_GPIO7>;
1145 clocks = <&cru PCLK_GPIO8>;
1598 clocks = <&cru ACLK_GPU>;
1603 clocks = <&cru ACLK_HEVC>,
1604 <&cru SCLK_HEVC_CABAC>,
1605 <&cru SCLK_HEVC_CORE>,
1606 <&cru HCLK_HEVC>;
1611 clocks = <&cru ACLK_IEP>,
1612 <&cru ACLK_ISP>,
1613 <&cru ACLK_RGA>,
1614 <&cru ACLK_VIP>,
1615 <&cru ACLK_VOP0>,
1616 <&cru ACLK_VOP1>,
1617 <&cru DCLK_VOP0>,
1618 <&cru DCLK_VOP1>,
1619 <&cru HCLK_IEP>,
1620 <&cru HCLK_ISP>,
1621 <&cru HCLK_RGA>,
1622 <&cru HCLK_VIP>,
1623 <&cru HCLK_VOP0>,
1624 <&cru HCLK_VOP1>,
1625 <&cru PCLK_EDP_CTRL>,
1626 <&cru PCLK_HDMI_CTRL>,
1627 <&cru PCLK_LVDS_PHY>,
1628 <&cru PCLK_MIPI_CSI>,
1629 <&cru PCLK_MIPI_DSI0>,
1630 <&cru PCLK_MIPI_DSI1>,
1631 <&cru SCLK_EDP_24M>,
1632 <&cru SCLK_EDP>,
1633 <&cru SCLK_HDMI_CEC>,
1634 <&cru SCLK_HDMI_HDCP>,
1635 <&cru SCLK_ISP_JPE>,
1636 <&cru SCLK_ISP>,
1637 <&cru SCLK_RGA>;
1642 clocks = <&cru ACLK_VCODEC>,
1643 <&cru HCLK_VCODEC>;