arm/dts/rk3288.dtsi

55 		#size-cells = <0>;
62 			reg = <0x500>;
87 			reg = <0x501>;
93 			reg = <0x502>;
99 			reg = <0x503>;
113 			reg = <0xff250000 0x4000>;
124 			reg = <0xff600000 0x4000>;
125 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 			reg = <0xffb20000 0x4000>;
137 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
149 		#clock-cells = <0>;
218 		fifo-depth = <0x100>;
221 		reg = <0xff0c0000 0x4000>;
231 		fifo-depth = <0x100>;
233 		reg = <0xff0d0000 0x4000>;
243 		fifo-depth = <0x100>;
245 		reg = <0xff0e0000 0x4000>;
255 		fifo-depth = <0x100>;
257 		reg = <0xff0f0000 0x4000>;
263 		reg = <0xff100000 0x100>;
279 		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
280 		reg = <0xff110000 0x1000>;
282 		#size-cells = <0>;
294 		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
295 		reg = <0xff120000 0x1000>;
297 		#size-cells = <0>;
309 		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
310 		reg = <0xff130000 0x1000>;
312 		#size-cells = <0>;
318 		reg = <0xff140000 0x1000>;
321 		#size-cells = <0>;
325 		pinctrl-0 = <&i2c1_xfer>;
331 		reg = <0xff150000 0x1000>;
334 		#size-cells = <0>;
338 		pinctrl-0 = <&i2c3_xfer>;
344 		reg = <0xff160000 0x1000>;
347 		#size-cells = <0>;
351 		pinctrl-0 = <&i2c4_xfer>;
357 		reg = <0xff170000 0x1000>;
360 		#size-cells = <0>;
364 		pinctrl-0 = <&i2c5_xfer>;
370 		reg = <0xff180000 0x100>;
378 		pinctrl-0 = <&uart0_xfer>;
384 		reg = <0xff190000 0x100>;
392 		pinctrl-0 = <&uart1_xfer>;
398 		reg = <0xff690000 0x100>;
406 		pinctrl-0 = <&uart2_xfer>;
411 		reg = <0xff1b0000 0x100>;
419 		pinctrl-0 = <&uart3_xfer>;
425 		reg = <0xff1c0000 0x100>;
433 		pinctrl-0 = <&uart4_xfer>;
443 		reg = <0xff280000 0x100>;
450 		pinctrl-0 = <&otp_out>;
458 		reg = <0xff290000 0x10000>;
474 		reg = <0xff500000 0x100>;
488 		reg = <0xff540000 0x40000>;
500 		reg = <0xff580000 0x40000>;
512 		reg = <0xff5c0000 0x100>;
526 		reg = <0xff610000 0x3fc
527 		       0xff620000 0x294
528 		       0xff630000 0x3fc
529 		       0xff640000 0x294>;
541 		reg = <0xff650000 0x1000>;
544 		#size-cells = <0>;
548 		pinctrl-0 = <&i2c0_xfer>;
554 		reg = <0xff660000 0x1000>;
557 		#size-cells = <0>;
561 		pinctrl-0 = <&i2c2_xfer>;
567 		reg = <0xff680000 0x10>;
570 		pinctrl-0 = <&pwm0_pin>;
579 		reg = <0xff680010 0x10>;
582 		pinctrl-0 = <&pwm1_pin>;
591 		reg = <0xff680020 0x10>;
594 		pinctrl-0 = <&pwm2_pin>;
603 		reg = <0xff680030 0x10>;
606 		pinctrl-0 = <&pwm3_pin>;
615 		reg = <0xff700000 0x18000>;
618 		ranges = <0 0xff700000 0x18000>;
619 		smp-sram@0 {
621 			reg = <0x00 0x10>;
625 			reg = <0x1000 0x4000>;
631 		reg = <0xff720000 0x1000>;
636 		reg = <0xff730000 0x100>;
641 		reg = <0xff740000 0x1000>;
646 		reg = <0xff760000 0x1000>;
664 		reg = <0xff770000 0x1000>;
669 		reg = <0xff800000 0x100>;
677 		reg = <0xff8b0000 0x10000>;
678 		#sound-dai-cells = <0>;
685 		pinctrl-0 = <&spdif_tx>;
692 		reg = <0xff890000 0x10000>;
695 		#size-cells = <0>;
696 		dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
701 		pinctrl-0 = <&i2s0_bus>;
707 		reg = <0xff8a0000 0x10000>;
717 		reg = <0xff930000 0x19c>;
728 			#size-cells = <0>;
729 			vopb_out_edp: endpoint@0 {
730 				reg = <0>;
751 		reg = <0xff930300 0x100>;
755 		#iommu-cells = <0>;
761 		reg = <0xff940000 0x19c>;
772 			#size-cells = <0>;
773 			vopl_out_edp: endpoint@0 {
774 				reg = <0>;
795 		reg = <0xff940300 0x100>;
799 		#iommu-cells = <0>;
805 		reg = <0xff970000 0x4000>;
816 			#size-cells = <0>;
820 				#size-cells = <0>;
821 				edp_in_vopb: endpoint@0 {
822 					reg = <0>;
835 		reg = <0xff980000 0x20000>;
842 		pinctrl-0 = <&hdmi_ddc>;
847 				#size-cells = <0>;
848 				hdmi_in_vopb: endpoint@0 {
849 					reg = <0>;
862 		reg = <0xff96c000 0x4000>;
866 		pinctrl-0 = <&lcdc0_ctl>;
871 			#size-cells = <0>;
872 			lvds_in: port@0 {
873 				reg = <0>;
875 				#size-cells = <0>;
876 				lvds_in_vopb: endpoint@0 {
877 					reg = <0>;
890 		reg = <0xff960000 0x4000>;
899 		#size-cells = <0>;
903 			#size-cells = <0>;
907 				#size-cells = <0>;
908 				dsi0_in_vopb: endpoint@0 {
909 					reg = <0>;
928 		reg = <0xff9a0000 0x800>;
940 		reg = <0xff9a0800 0x100>;
944 		#iommu-cells = <0>;
952 		reg = <0xffa30000 0x10000>;
974 		reg = <0xffac0000 0x2000>;
979 		reg = <0xffb40000 0x10000>;
987 		#address-cells = <0>;
989 		reg = <0xffc01000 0x1000>,
990 		      <0xffc02000 0x1000>,
991 		      <0xffc04000 0x2000>,
992 		      <0xffc06000 0x2000>;
993 		interrupts = <GIC_PPI 9 0xf04>;
1004 		#size-cells = <0>;
1008 			#phy-cells = <0>;
1009 			reg = <0x320>;
1015 			#phy-cells = <0>;
1016 			reg = <0x334>;
1022 			#phy-cells = <0>;
1023 			reg = <0x348>;
1039 			reg =	<0xff750000 0x100>;
1052 			reg = <0xff780000 0x100>;
1065 			reg = <0xff790000 0x100>;
1078 			reg = <0xff7a0000 0x100>;
1091 			reg = <0xff7b0000 0x100>;
1104 			reg = <0xff7c0000 0x100>;
1117 			reg = <0xff7d0000 0x100>;
1130 			reg = <0xff7e0000 0x100>;
1143 			reg = <0xff7f0000 0x100>;
1180 				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1184 				rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1188 				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1192 				rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1198 				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1199 						<0 16 RK_FUNC_1 &pcfg_pull_none>;
1240 				rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1379 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1383 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1390 				rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1521 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1527 				rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1559 						<4 0 3 &pcfg_pull_none>,
1573 						<4 0 3 &pcfg_pull_none>,
1594 		#size-cells = <0>;