arm/dts/rk322x.dtsi

4  * SPDX-License-Identifier:	GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3228-cru.h>
12 #include <dt-bindings/thermal/thermal.h>
15 	#address-cells = <1>;
16 	#size-cells = <1>;
18 	interrupt-parent = <&gic>;
29 		#address-cells = <1>;
30 		#size-cells = <0>;
34 			compatible = "arm,cortex-a7";
37 			operating-points = <
41 			#cooling-cells = <2>; /* min followed by max */
42 			clock-latency = <40000>;
48 			compatible = "arm,cortex-a7";
55 			compatible = "arm,cortex-a7";
62 			compatible = "arm,cortex-a7";
69 		compatible = "simple-bus";
70 		#address-cells = <1>;
71 		#size-cells = <1>;
79 			#dma-cells = <1>;
81 			clock-names = "apb_pclk";
85 	arm-pmu {
86 		compatible = "arm,cortex-a7-pmu";
91 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
100 		compatible      = "arm,psci-1.0";
105 		compatible = "arm,armv7-timer";
106 		arm,cpu-registers-not-fw-configured;
111 		clock-frequency = <24000000>;
115 		compatible = "fixed-clock";
116 		clock-frequency = <24000000>;
117 		clock-output-names = "xin24m";
118 		#clock-cells = <0>;
122 		compatible = "mmio-sram";
124 		#address-cells = <1>;
125 		#size-cells = <1>;
127 		smp-sram@0 {
128 			compatible = "rockchip,rk322x-smp-sram";
131 		ddr_sram: ddr-sram@1000 {
132 			compatible = "rockchip,rk322x-ddr-sram";
138 		compatible = "rockchip,rk322x-crypto";
140 		clock-names = "sclk_crypto";
146 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
149 		#address-cells = <1>;
150 		#size-cells = <0>;
151 		clock-names = "i2s_clk", "i2s_hclk";
154 		dma-names = "tx", "rx";
155 		pinctrl-names = "default";
156 		pinctrl-0 = <&i2s1_bus>;
161 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
164 		#address-cells = <1>;
165 		#size-cells = <0>;
166 		clock-names = "i2s_clk", "i2s_hclk";
169 		dma-names = "tx", "rx";
174 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
177 		#address-cells = <1>;
178 		#size-cells = <0>;
179 		clock-names = "i2s_clk", "i2s_hclk";
182 		dma-names = "tx", "rx";
187 		compatible = "rockchip,rk3228-grf", "syscon";
189 		#address-cells = <1>;
190 		#size-cells = <1>;
192 		u2phy0: usb2-phy@760 {
193 			compatible = "rockchip,rk322x-usb2phy";
197 			u2phy0_otg: otg-port {
198 				#phy-cells = <0>;
202 				interrupt-names = "otg-bvalid", "otg-id",
207 			u2phy0_host: host-port {
208 				#phy-cells = <0>;
210 				interrupt-names = "linestate";
215 		u2phy1: usb2-phy@800 {
216 			compatible = "rockchip,rk322x-usb2phy";
220 			u2phy1_otg: otg-port {
221 				#phy-cells = <0>;
223 				interrupt-names = "linestate";
227 			u2phy1_host: host-port {
228 				#phy-cells = <0>;
230 				interrupt-names = "linestate";
237 		compatible = "snps,dw-apb-uart";
240 		clock-frequency = <24000000>;
242 		clock-names = "baudclk", "apb_pclk";
243 		pinctrl-names = "default";
244 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
245 		reg-shift = <2>;
246 		reg-io-width = <4>;
251 		compatible = "snps,dw-apb-uart";
254 		clock-frequency = <24000000>;
256 		clock-names = "baudclk", "apb_pclk";
257 		pinctrl-names = "default";
258 		pinctrl-0 = <&uart1_xfer>;
259 		reg-shift = <2>;
260 		reg-io-width = <4>;
265 		compatible = "snps,dw-apb-uart";
268 		clock-frequency = <24000000>;
270 		clock-names = "baudclk", "apb_pclk";
271 		pinctrl-names = "default";
272 		pinctrl-0 = <&uart21_xfer>;
273 		reg-shift = <2>;
274 		reg-io-width = <4>;
279 		compatible = "rockchip,rk322x-efuse";
281 		#address-cells = <1>;
282 		#size-cells = <1>;
284 		clock-names = "pclk_efuse";
296 		compatible = "rockchip,rk3228-i2c";
299 		#address-cells = <1>;
300 		#size-cells = <0>;
301 		clock-names = "i2c";
303 		pinctrl-names = "default";
304 		pinctrl-0 = <&i2c0_xfer>;
309 		compatible = "rockchip,rk3228-i2c";
312 		#address-cells = <1>;
313 		#size-cells = <0>;
314 		clock-names = "i2c";
316 		pinctrl-names = "default";
317 		pinctrl-0 = <&i2c1_xfer>;
322 		compatible = "rockchip,rk3228-i2c";
325 		#address-cells = <1>;
326 		#size-cells = <0>;
327 		clock-names = "i2c";
329 		pinctrl-names = "default";
330 		pinctrl-0 = <&i2c2_xfer>;
335 		compatible = "rockchip,rk3228-i2c";
338 		#address-cells = <1>;
339 		#size-cells = <0>;
340 		clock-names = "i2c";
342 		pinctrl-names = "default";
343 		pinctrl-0 = <&i2c3_xfer>;
348 		compatible = "rockchip,rk3288-pwm";
350 		#pwm-cells = <3>;
352 		clock-names = "pwm";
353 		pinctrl-names = "active";
354 		pinctrl-0 = <&pwm0_pin>;
359 		compatible = "rockchip,rk3288-pwm";
361 		#pwm-cells = <3>;
363 		clock-names = "pwm";
364 		pinctrl-names = "active";
365 		pinctrl-0 = <&pwm1_pin>;
370 		compatible = "rockchip,rk3288-pwm";
372 		#pwm-cells = <3>;
374 		clock-names = "pwm";
375 		pinctrl-names = "active";
376 		pinctrl-0 = <&pwm2_pin>;
381 		compatible = "rockchip,rk3288-pwm";
383 		#pwm-cells = <2>;
385 		clock-names = "pwm";
386 		pinctrl-names = "active";
387 		pinctrl-0 = <&pwm3_pin>;
392 		compatible = "rockchip,rk3288-timer";
396 		clock-names = "timer", "pclk";
399 	cru: clock-controller@110e0000 {
400 		compatible = "rockchip,rk3228-cru";
403 		#clock-cells = <1>;
404 		#reset-cells = <1>;
405 		assigned-clocks = <&cru PLL_GPLL>;
406 		assigned-clock-rates = <594000000>;
409 	thermal-zones {
410 		cpu_thermal: cpu-thermal {
411 			polling-delay-passive = <100>; /* milliseconds */
412 			polling-delay = <5000>; /* milliseconds */
414 			thermal-sensors = <&tsadc 0>;
434 			cooling-maps {
437 					cooling-device =
442 					cooling-device =
450 		compatible = "rockchip,rk3228-tsadc";
454 		clock-names = "tsadc", "apb_pclk";
456 		reset-names = "tsadc-apb";
457 		pinctrl-names = "init", "default", "sleep";
458 		pinctrl-0 = <&otp_gpio>;
459 		pinctrl-1 = <&otp_out>;
460 		pinctrl-2 = <&otp_gpio>;
461 		#thermal-sensor-cells = <0>;
462 		rockchip,hw-tshut-temp = <95000>;
467 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
469 		max-frequency = <150000000>;
473 		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
474 		fifo-depth = <0x100>;
475 		cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
476 		pinctrl-names = "default";
477 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
482 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
487 		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
488 		fifo-depth = <0x100>;
489 		pinctrl-names = "default";
490 		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
495 		compatible = "rockchip,rk3288-dw-mshc";
497 		max-frequency = <150000000>;
501 		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
502 		bus-width = <8>;
503 		default-sample-phase = <158>;
504 		num-slots = <1>;
505 		fifo-depth = <0x100>;
506 		pinctrl-names = "default";
507 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
509 		reset-names = "reset";
514 		compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
518 		hnp-srp-disable;
521 		phy-names = "usb2-phy";
526 		compatible = "rockchip,rk3228-gmac";
529 		interrupt-names = "macirq";
534 		clock-names = "stmmaceth", "mac_clk_rx",
539 		reset-names = "stmmaceth", "mac-phy";
544 	gic: interrupt-controller@32010000 {
545 		compatible = "arm,gic-400";
546 		interrupt-controller;
547 		#interrupt-cells = <3>;
548 		#address-cells = <0>;
558 		compatible = "rockchip,rk3228-pinctrl";
560 		#address-cells = <1>;
561 		#size-cells = <1>;
565 			compatible = "rockchip,gpio-bank";
570 			gpio-controller;
571 			#gpio-cells = <2>;
573 			interrupt-controller;
574 			#interrupt-cells = <2>;
578 			compatible = "rockchip,gpio-bank";
583 			gpio-controller;
584 			#gpio-cells = <2>;
586 			interrupt-controller;
587 			#interrupt-cells = <2>;
591 			compatible = "rockchip,gpio-bank";
596 			gpio-controller;
597 			#gpio-cells = <2>;
599 			interrupt-controller;
600 			#interrupt-cells = <2>;
604 			compatible = "rockchip,gpio-bank";
609 			gpio-controller;
610 			#gpio-cells = <2>;
612 			interrupt-controller;
613 			#interrupt-cells = <2>;
616 		pcfg_pull_up: pcfg-pull-up {
617 			bias-pull-up;
620 		pcfg_pull_down: pcfg-pull-down {
621 			bias-pull-down;
624 		pcfg_pull_none: pcfg-pull-none {
625 			bias-disable;
628 		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
629 			drive-strength = <12>;
633 			sdmmc_clk: sdmmc-clk {
637 			sdmmc_cmd: sdmmc-cmd {
641 			sdmmc_bus4: sdmmc-bus4 {
650 			sdio_clk: sdio-clk {
654 			sdio_cmd: sdio-cmd {
658 			sdio_bus4: sdio-bus4 {
667 			emmc_clk: emmc-clk {
671 			emmc_cmd: emmc-cmd {
675 			emmc_bus8: emmc-bus8 {
688 			rgmii_pins: rgmii-pins {
706 			rmii_pins: rmii-pins {
719 			phy_pins: phy-pins {
726 			i2c0_xfer: i2c0-xfer {
733 			i2c1_xfer: i2c1-xfer {
740 			i2c2_xfer: i2c2-xfer {
747 			i2c3_xfer: i2c3-xfer {
754 			i2s1_bus: i2s1-bus {
768 			pwm0_pin: pwm0-pin {
774 			pwm1_pin: pwm1-pin {
780 			pwm2_pin: pwm2-pin {
786 			pwm3_pin: pwm3-pin {
792 			otp_gpio: otp-gpio {
796 			otp_out: otp-out {
802 			uart0_xfer: uart0-xfer {
807 			uart0_cts: uart0-cts {
811 			uart0_rts: uart0-rts {
817 			uart1_xfer: uart1-xfer {
822 			uart1_cts: uart1-cts {
826 			uart1_rts: uart1-rts {
832 			uart2_xfer: uart2-xfer {
837 			uart2_cts: uart2-cts {
841 			uart2_rts: uart2-rts {
846 		uart2-1 {
847 			uart21_xfer: uart21-xfer {
855 		compatible = "rockchip,rk3228-dmc", "syscon";
861 		rockchip,sram = <&ddr_sram>;
865 		compatible = "rockchip,rk3228-msch", "syscon";
870 		compatible = "rockchip,rk-nandc";
875 		clock-names = "clk_nandc", "hclk_nandc";