arm/dts/rk3188.dtsi

5  * SPDX-License-Identifier:     GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
17 		#address-cells = <1>;
18 		#size-cells = <0>;
19 		enable-method = "rockchip,rk3066-smp";
23 			compatible = "arm,cortex-a9";
24 			next-level-cache = <&L2>;
26 			operating-points = <
37 			clock-latency = <40000>;
42 			compatible = "arm,cortex-a9";
43 			next-level-cache = <&L2>;
48 			compatible = "arm,cortex-a9";
49 			next-level-cache = <&L2>;
54 			compatible = "arm,cortex-a9";
55 			next-level-cache = <&L2>;
61 		compatible = "mmio-sram";
63 		#address-cells = <1>;
64 		#size-cells = <1>;
67 		smp-sram@0 {
68 			compatible = "rockchip,rk3066-smp-sram";
74 		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
77 		#address-cells = <1>;
78 		#size-cells = <0>;
79 		pinctrl-names = "default";
80 		pinctrl-0 = <&i2s0_bus>;
82 		dma-names = "tx", "rx";
83 		clock-names = "i2s_hclk", "i2s_clk";
85 		rockchip,playback-channels = <2>;
86 		rockchip,capture-channels = <2>;
91 		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
93 		#sound-dai-cells = <0>;
94 		clock-names = "hclk", "mclk";
97 		dma-names = "tx";
99 		pinctrl-names = "default";
100 		pinctrl-0 = <&spdif_tx>;
104 	cru: clock-controller@20000000 {
105 		compatible = "rockchip,rk3188-cru";
109 		#clock-cells = <1>;
110 		#reset-cells = <1>;
114 		compatible = "rockchip,rockchip-efuse";
116 		#address-cells = <1>;
117 		#size-cells = <1>;
119 		clock-names = "pclk_efuse";
130 		#io-channel-cells = <1>;
132 		clock-names = "saradc", "pclk_saradc";
137 		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
143 		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
145 		#address-cells = <1>;
146 		#size-cells = <0>;
149 		usbphy0: usb-phy@10c {
150 			#phy-cells = <0>;
153 			clock-names = "phyclk";
154 			#clock-cells = <0>;
157 		usbphy1: usb-phy@11c {
158 			#phy-cells = <0>;
161 			clock-names = "phyclk";
162 			#clock-cells = <0>;
167 		compatible = "rockchip,rk3188-pinctrl";
171 		#address-cells = <1>;
172 		#size-cells = <1>;
176 			compatible = "rockchip,gpio-bank";
181 			gpio-controller;
182 			#gpio-cells = <2>;
184 			interrupt-controller;
185 			#interrupt-cells = <2>;
189 			compatible = "rockchip,gpio-bank";
194 			gpio-controller;
195 			#gpio-cells = <2>;
197 			interrupt-controller;
198 			#interrupt-cells = <2>;
202 			compatible = "rockchip,gpio-bank";
207 			gpio-controller;
208 			#gpio-cells = <2>;
210 			interrupt-controller;
211 			#interrupt-cells = <2>;
215 			compatible = "rockchip,gpio-bank";
220 			gpio-controller;
221 			#gpio-cells = <2>;
223 			interrupt-controller;
224 			#interrupt-cells = <2>;
228 			bias-pull-up;
232 			bias-pull-down;
236 			bias-disable;
240 			emmc_clk: emmc-clk {
244 			emmc_cmd: emmc-cmd {
248 			emmc_rst: emmc-rst {
256 			 * flash/emmc is the boot-device.
261 			emac_xfer: emac-xfer {
272 			emac_mdio: emac-mdio {
279 			i2c0_xfer: i2c0-xfer {
286 			i2c1_xfer: i2c1-xfer {
293 			i2c2_xfer: i2c2-xfer {
300 			i2c3_xfer: i2c3-xfer {
307 			i2c4_xfer: i2c4-xfer {
314 			pwm0_out: pwm0-out {
320 			pwm1_out: pwm1-out {
326 			pwm2_out: pwm2-out {
332 			pwm3_out: pwm3-out {
338 			spi0_clk: spi0-clk {
341 			spi0_cs0: spi0-cs0 {
344 			spi0_tx: spi0-tx {
347 			spi0_rx: spi0-rx {
350 			spi0_cs1: spi0-cs1 {
356 			spi1_clk: spi1-clk {
359 			spi1_cs0: spi1-cs0 {
362 			spi1_rx: spi1-rx {
365 			spi1_tx: spi1-tx {
368 			spi1_cs1: spi1-cs1 {
374 			uart0_xfer: uart0-xfer {
379 			uart0_cts: uart0-cts {
383 			uart0_rts: uart0-rts {
389 			uart1_xfer: uart1-xfer {
394 			uart1_cts: uart1-cts {
398 			uart1_rts: uart1-rts {
404 			uart2_xfer: uart2-xfer {
412 			uart3_xfer: uart3-xfer {
417 			uart3_cts: uart3-cts {
421 			uart3_rts: uart3-rts {
427 			sd0_clk: sd0-clk {
431 			sd0_cmd: sd0-cmd {
435 			sd0_cd: sd0-cd {
439 			sd0_wp: sd0-wp {
443 			sd0_pwr: sd0-pwr {
447 			sd0_bus1: sd0-bus-width1 {
451 			sd0_bus4: sd0-bus-width4 {
460 			sd1_clk: sd1-clk {
464 			sd1_cmd: sd1-cmd {
468 			sd1_cd: sd1-cd {
472 			sd1_wp: sd1-wp {
476 			sd1_bus1: sd1-bus-width1 {
480 			sd1_bus4: sd1-bus-width4 {
489 			i2s0_bus: i2s0-bus {
500 			spdif_tx: spdif-tx {
508 	compatible = "rockchip,rk3188-emac";
516 	compatible = "rockchip,rk3188-grf", "syscon";
524 	compatible = "rockchip,rk3188-i2c";
525 	pinctrl-names = "default";
526 	pinctrl-0 = <&i2c0_xfer>;
530 	compatible = "rockchip,rk3188-i2c";
531 	pinctrl-names = "default";
532 	pinctrl-0 = <&i2c1_xfer>;
536 	compatible = "rockchip,rk3188-i2c";
537 	pinctrl-names = "default";
538 	pinctrl-0 = <&i2c2_xfer>;
542 	compatible = "rockchip,rk3188-i2c";
543 	pinctrl-names = "default";
544 	pinctrl-0 = <&i2c3_xfer>;
548 	compatible = "rockchip,rk3188-i2c";
549 	pinctrl-names = "default";
550 	pinctrl-0 = <&i2c4_xfer>;
554 	compatible = "rockchip,rk3188-pmu", "syscon";
558 	pinctrl-names = "active";
559 	pinctrl-0 = <&pwm0_out>;
563 	pinctrl-names = "active";
564 	pinctrl-0 = <&pwm1_out>;
568 	pinctrl-names = "active";
569 	pinctrl-0 = <&pwm2_out>;
573 	pinctrl-names = "active";
574 	pinctrl-0 = <&pwm3_out>;
578 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
579 	pinctrl-names = "default";
580 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
584 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
585 	pinctrl-names = "default";
586 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
590 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
591 	pinctrl-names = "default";
592 	pinctrl-0 = <&uart0_xfer>;
596 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
597 	pinctrl-names = "default";
598 	pinctrl-0 = <&uart1_xfer>;
602 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
603 	pinctrl-names = "default";
604 	pinctrl-0 = <&uart2_xfer>;
608 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
609 	pinctrl-names = "default";
610 	pinctrl-0 = <&uart3_xfer>;
614 	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";