arm/dts/rk3066a.dtsi

5  * SPDX-License-Identifier:	GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3066a-cru.h>
17 		#address-cells = <1>;
18 		#size-cells = <0>;
19 		enable-method = "rockchip,rk3066-smp";
23 			compatible = "arm,cortex-a9";
24 			next-level-cache = <&L2>;
26 			operating-points = <
36 			clock-latency = <40000>;
41 			compatible = "arm,cortex-a9";
42 			next-level-cache = <&L2>;
47 	sram: sram@10080000 {  label
48 		compatible = "mmio-sram";
50 		#address-cells = <1>;
51 		#size-cells = <1>;
54 		smp-sram@0 {
55 			compatible = "rockchip,rk3066-smp-sram";
61 		compatible = "rockchip,rk3066-i2s";
64 		#address-cells = <1>;
65 		#size-cells = <0>;
66 		pinctrl-names = "default";
67 		pinctrl-0 = <&i2s0_bus>;
69 		dma-names = "tx", "rx";
70 		clock-names = "i2s_hclk", "i2s_clk";
72 		rockchip,playback-channels = <8>;
73 		rockchip,capture-channels = <2>;
78 		compatible = "rockchip,rk3066-i2s";
81 		#address-cells = <1>;
82 		#size-cells = <0>;
83 		pinctrl-names = "default";
84 		pinctrl-0 = <&i2s1_bus>;
86 		dma-names = "tx", "rx";
87 		clock-names = "i2s_hclk", "i2s_clk";
89 		rockchip,playback-channels = <2>;
90 		rockchip,capture-channels = <2>;
95 		compatible = "rockchip,rk3066-i2s";
98 		#address-cells = <1>;
99 		#size-cells = <0>;
100 		pinctrl-names = "default";
101 		pinctrl-0 = <&i2s2_bus>;
103 		dma-names = "tx", "rx";
104 		clock-names = "i2s_hclk", "i2s_clk";
106 		rockchip,playback-channels = <2>;
107 		rockchip,capture-channels = <2>;
115 		clock-names = "hclk";
120 	cru: clock-controller@20000000 {
121 		compatible = "rockchip,rk3066a-cru";
124 		u-boot,dm-pre-reloc;
126 		#clock-cells = <1>;
127 		#reset-cells = <1>;
128 		assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
132 		assigned-clock-rates = <400000000>, <594000000>,
139 		compatible = "snps,dw-apb-timer-osc";
143 		clock-names = "timer", "pclk";
147 		compatible = "rockchip,rk3066a-efuse";
149 		#address-cells = <1>;
150 		#size-cells = <1>;
152 		clock-names = "pclk_efuse";
160 		compatible = "snps,dw-apb-timer-osc";
164 		clock-names = "timer", "pclk";
168 		compatible = "snps,dw-apb-timer-osc";
172 		clock-names = "timer", "pclk";
176 		compatible = "rockchip,rk3066-tsadc";
179 		clock-names = "saradc", "apb_pclk";
181 		#io-channel-cells = <1>;
183 		reset-names = "saradc-apb";
188 		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
190 		#address-cells = <1>;
191 		#size-cells = <0>;
194 		usbphy0: usb-phy@17c {
195 			#phy-cells = <0>;
198 			clock-names = "phyclk";
199 			#clock-cells = <0>;
202 		usbphy1: usb-phy@188 {
203 			#phy-cells = <0>;
206 			clock-names = "phyclk";
207 			#clock-cells = <0>;
212 		compatible = "rockchip,rk3066a-pinctrl";
214 		#address-cells = <1>;
215 		#size-cells = <1>;
217 		u-boot,dm-pre-reloc;
220 			compatible = "rockchip,gpio-bank";
225 			gpio-controller;
226 			#gpio-cells = <2>;
228 			interrupt-controller;
229 			#interrupt-cells = <2>;
233 			compatible = "rockchip,gpio-bank";
238 			gpio-controller;
239 			#gpio-cells = <2>;
241 			interrupt-controller;
242 			#interrupt-cells = <2>;
246 			compatible = "rockchip,gpio-bank";
251 			gpio-controller;
252 			#gpio-cells = <2>;
254 			interrupt-controller;
255 			#interrupt-cells = <2>;
259 			compatible = "rockchip,gpio-bank";
264 			gpio-controller;
265 			#gpio-cells = <2>;
267 			interrupt-controller;
268 			#interrupt-cells = <2>;
272 			compatible = "rockchip,gpio-bank";
277 			gpio-controller;
278 			#gpio-cells = <2>;
280 			interrupt-controller;
281 			#interrupt-cells = <2>;
285 			compatible = "rockchip,gpio-bank";
290 			gpio-controller;
291 			#gpio-cells = <2>;
293 			interrupt-controller;
294 			#interrupt-cells = <2>;
298 			bias-pull-pin-default;
302 			bias-disable;
306 			emac_xfer: emac-xfer {
317 			emac_mdio: emac-mdio {
324 			emmc_clk: emmc-clk {
328 			emmc_cmd: emmc-cmd {
332 			emmc_rst: emmc-rst {
340 			 * flash/emmc is the boot-device.
345 			i2c0_xfer: i2c0-xfer {
352 			i2c1_xfer: i2c1-xfer {
359 			i2c2_xfer: i2c2-xfer {
366 			i2c3_xfer: i2c3-xfer {
373 			i2c4_xfer: i2c4-xfer {
380 			pwm0_out: pwm0-out {
386 			pwm1_out: pwm1-out {
392 			pwm2_out: pwm2-out {
398 			pwm3_out: pwm3-out {
404 			spi0_clk: spi0-clk {
407 			spi0_cs0: spi0-cs0 {
410 			spi0_tx: spi0-tx {
413 			spi0_rx: spi0-rx {
416 			spi0_cs1: spi0-cs1 {
422 			spi1_clk: spi1-clk {
425 			spi1_cs0: spi1-cs0 {
428 			spi1_rx: spi1-rx {
431 			spi1_tx: spi1-tx {
434 			spi1_cs1: spi1-cs1 {
440 			uart0_xfer: uart0-xfer {
445 			uart0_cts: uart0-cts {
449 			uart0_rts: uart0-rts {
455 			uart1_xfer: uart1-xfer {
460 			uart1_cts: uart1-cts {
464 			uart1_rts: uart1-rts {
470 			uart2_xfer: uart2-xfer {
478 			uart3_xfer: uart3-xfer {
483 			uart3_cts: uart3-cts {
487 			uart3_rts: uart3-rts {
493 			sd0_clk: sd0-clk {
497 			sd0_cmd: sd0-cmd {
501 			sd0_cd: sd0-cd {
505 			sd0_wp: sd0-wp {
509 			sd0_bus1: sd0-bus-width1 {
513 			sd0_bus4: sd0-bus-width4 {
522 			sd1_clk: sd1-clk {
526 			sd1_cmd: sd1-cmd {
530 			sd1_cd: sd1-cd {
534 			sd1_wp: sd1-wp {
538 			sd1_bus1: sd1-bus-width1 {
542 			sd1_bus4: sd1-bus-width4 {
551 			i2s0_bus: i2s0-bus {
565 			i2s1_bus: i2s1-bus {
576 			i2s2_bus: i2s2-bus {
589 	compatible = "rockchip,rk3066-grf", "syscon";
593 	pinctrl-names = "default";
594 	pinctrl-0 = <&i2c0_xfer>;
598 	pinctrl-names = "default";
599 	pinctrl-0 = <&i2c1_xfer>;
603 	pinctrl-names = "default";
604 	pinctrl-0 = <&i2c2_xfer>;
608 	pinctrl-names = "default";
609 	pinctrl-0 = <&i2c3_xfer>;
613 	pinctrl-names = "default";
614 	pinctrl-0 = <&i2c4_xfer>;
618 	clock-frequency = <50000000>;
620 	dma-names = "rx-tx";
621 	max-frequency = <50000000>;
622 	pinctrl-names = "default";
623 	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
624 	u-boot,dm-pre-reloc;
629 	dma-names = "rx-tx";
630 	pinctrl-names = "default";
631 	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
636 	dma-names = "rx-tx";
640 	pinctrl-names = "active";
641 	pinctrl-0 = <&pwm0_out>;
645 	pinctrl-names = "active";
646 	pinctrl-0 = <&pwm1_out>;
650 	pinctrl-names = "active";
651 	pinctrl-0 = <&pwm2_out>;
655 	pinctrl-names = "active";
656 	pinctrl-0 = <&pwm3_out>;
660 	pinctrl-names = "default";
661 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
665 	pinctrl-names = "default";
666 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
670 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
672 	dma-names = "tx", "rx";
673 	pinctrl-names = "default";
674 	pinctrl-0 = <&uart0_xfer>;
678 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
680 	dma-names = "tx", "rx";
681 	pinctrl-names = "default";
682 	pinctrl-0 = <&uart1_xfer>;
686 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
688 	dma-names = "tx", "rx";
689 	pinctrl-names = "default";
690 	pinctrl-0 = <&uart2_xfer>;
694 	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
696 	dma-names = "tx", "rx";
697 	pinctrl-names = "default";
698 	pinctrl-0 = <&uart3_xfer>;
702 	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
706 	compatible = "rockchip,rk3066-emac";