Lines Matching +full:usb +full:- +full:grf
2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3036-cru.h>
15 interrupt-parent = <&gic>;
34 arm-pmu {
35 compatible = "arm,cortex-a7-pmu";
38 interrupt-affinity = <&cpu0>, <&cpu1>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "rockchip,rk3036-smp";
48 compatible = "arm,cortex-a7";
50 operating-points = <
54 #cooling-cells = <2>; /* min followed by max */
55 clock-latency = <40000>;
61 compatible = "arm,cortex-a7";
68 compatible = "arm,amba-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
76 arm,pl330-broken-no-flushp;
79 #dma-cells = <1>;
81 clock-names = "apb_pclk";
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 clock-output-names = "xin24m";
89 #clock-cells = <0>;
93 compatible = "arm,psci-1.0";
98 compatible = "arm,armv7-timer";
99 arm,cpu-registers-not-fw-configured;
104 clock-frequency = <24000000>;
107 cru: clock-controller@20000000 {
108 compatible = "rockchip,rk3036-cru";
110 rockchip,grf = <&grf>;
111 #clock-cells = <1>;
112 #reset-cells = <1>;
113 assigned-clocks = <&cru PLL_GPLL>;
114 assigned-clock-rates = <594000000>;
118 compatible = "rockchip,rk3036-dmc", "syscon";
123 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
126 reg-shift = <2>;
127 reg-io-width = <4>;
128 clock-frequency = <24000000>;
130 clock-names = "baudclk", "apb_pclk";
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
136 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
139 reg-shift = <2>;
140 reg-io-width = <4>;
141 clock-frequency = <24000000>;
143 clock-names = "baudclk", "apb_pclk";
144 pinctrl-names = "default";
145 pinctrl-0 = <&uart1_xfer>;
149 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
152 reg-shift = <2>;
153 reg-io-width = <4>;
154 clock-frequency = <24000000>;
156 clock-names = "baudclk", "apb_pclk";
157 pinctrl-names = "default";
158 pinctrl-0 = <&uart2_xfer>;
162 compatible = "rockchip,rk2928-pwm";
164 #pwm-cells = <3>;
165 pinctrl-names = "active";
166 pinctrl-0 = <&pwm0_pin>;
168 clock-names = "pwm";
173 compatible = "rockchip,rk2928-pwm";
175 #pwm-cells = <3>;
176 pinctrl-names = "active";
177 pinctrl-0 = <&pwm1_pin>;
179 clock-names = "pwm";
184 compatible = "rockchip,rk2928-pwm";
186 #pwm-cells = <3>;
187 pinctrl-names = "active";
188 pinctrl-0 = <&pwm2_pin>;
190 clock-names = "pwm";
195 compatible = "rockchip,rk2928-pwm";
197 #pwm-cells = <2>;
198 pinctrl-names = "active";
199 pinctrl-0 = <&pwm3_pin>;
201 clock-names = "pwm";
206 compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
210 gic: interrupt-controller@10139000 {
211 compatible = "arm,gic-400";
212 interrupt-controller;
213 #interrupt-cells = <3>;
214 #address-cells = <0>;
223 grf: syscon@20008000 { label
224 compatible = "rockchip,rk3036-grf", "syscon";
226 #address-cells = <1>;
227 #size-cells = <1>;
229 usb2phy: usb2-phy@17c {
230 compatible = "rockchip,rk3036-usb2phy";
233 clock-names = "phyclk";
234 #clock-cells = <0>;
235 clock-output-names = "usb480m_phy";
238 u2phy_otg: otg-port {
239 #phy-cells = <0>;
243 interrupt-names = "otg-bvalid", "otg-id",
248 u2phy_host: host-port {
249 #phy-cells = <0>;
251 interrupt-names = "linestate";
257 usb_otg: usb@10180000 {
258 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
263 clock-names = "otg";
265 g-np-tx-fifo-size = <16>;
266 g-rx-fifo-size = <275>;
267 g-tx-fifo-size = <256 128 128 64 64 32>;
268 g-use-dma;
272 usb_host: usb@101c0000 {
273 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
278 clock-names = "otg";
284 compatible = "rockchip,rk3288-dw-mshc";
285 clock-frequency = <37500000>;
286 max-frequency = <37500000>;
289 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
291 dma-names = "rx-tx";
292 fifo-depth = <0x100>;
295 broken-cd;
296 bus-width = <8>;
297 cap-mmc-highspeed;
298 mmc-ddr-1_8v;
299 disable-wp;
300 fifo-mode;
301 non-removable;
302 num-slots = <1>;
303 default-sample-phase = <158>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
311 #address-cells = <1>;
312 #size-cells = <0>;
315 clock-names = "clk_sfc", "hclk_sfc";
320 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
322 clock-frequency = <37500000>;
323 max-frequency = <37500000>;
325 clock-names = "biu", "ciu";
326 fifo-depth = <0x100>;
332 compatible = "rockchip,rk-nandc";
337 clock-names = "clk_nandc", "hclk_nandc";
342 compatible = "rockchip,rk3036-pinctrl";
343 rockchip,grf = <&grf>;
344 #address-cells = <1>;
345 #size-cells = <1>;
349 compatible = "rockchip,gpio-bank";
354 gpio-controller;
355 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
362 compatible = "rockchip,gpio-bank";
367 gpio-controller;
368 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
375 compatible = "rockchip,gpio-bank";
380 gpio-controller;
381 #gpio-cells = <2>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
387 pcfg_pull_up: pcfg-pull-up {
388 bias-pull-up;
391 pcfg_pull_down: pcfg-pull-down {
392 bias-pull-down;
395 pcfg_pull_none: pcfg-pull-none {
396 bias-disable;
404 emmc_clk: emmc-clk {
408 emmc_cmd: emmc-cmd {
412 emmc_bus8: emmc-bus8 {
427 uart0_xfer: uart0-xfer {
432 uart0_cts: uart0-cts {
436 uart0_rts: uart0-rts {
442 uart1_xfer: uart1-xfer {
450 uart2_xfer: uart2-xfer {
458 pwm0_pin: pwm0-pin {
464 pwm1_pin: pwm1-pin {
470 pwm2_pin: pwm2-pin {
476 pwm3_pin: pwm3-pin {
482 i2c1_xfer: i2c1-xfer {
490 compatible = "rockchip,rk3288-i2c";
493 #address-cells = <1>;
494 #size-cells = <0>;
495 clock-names = "i2c";
497 pinctrl-names = "default";
498 pinctrl-0 = <&i2c1_xfer>;