Lines Matching +full:sfc +full:- +full:no +full:- +full:dma
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/clock/rk1808-cru.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/power/rk1808-power.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35", "arm,armv8";
50 compatible = "arm,cortex-a35", "arm,armv8";
56 arm-pmu {
57 compatible = "arm,cortex-a53-pmu";
60 interrupt-affinity = <&cpu0>, <&cpu1>;
64 compatible = "rockchip,rk1808-dmc";
67 gmac_clkin: external-gmac-clock {
68 compatible = "fixed-clock";
69 clock-frequency = <125000000>;
70 clock-output-names = "gmac_clkin";
71 #clock-cells = <0>;
75 compatible = "arm,armv8-timer";
80 arm,no-tick-in-suspend;
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m";
87 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <32768>;
93 clock-output-names = "xin32k";
94 #clock-cells = <0>;
98 compatible = "rockchip,rk1808-dwc3";
101 clock-names = "ref_clk", "bus_clk",
103 #address-cells = <2>;
104 #size-cells = <2>;
114 phy-names = "usb2-phy";
117 snps,dis-u2-freeclk-exists-quirk;
119 snps,dis-del-phy-power-chg-quirk;
120 snps,tx-ipgap-linecheck-dis-quirk;
126 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd";
128 #address-cells = <1>;
129 #size-cells = <1>;
131 io_domains: io-domains {
132 compatible = "rockchip,rk1808-io-voltage-domain";
137 compatible = "rockchip,rk1808-rgb";
141 #address-cells = <1>;
142 #size-cells = <0>;
148 remote-endpoint = <&vop_lite_out_rgb>;
156 compatible = "rockchip,rk1808-usb2phy-grf", "syscon",
157 "simple-mfd";
159 #address-cells = <1>;
160 #size-cells = <1>;
162 u2phy: usb2-phy@100 {
163 compatible = "rockchip,rk1808-usb2phy";
166 clock-names = "phyclk";
167 #clock-cells = <0>;
168 assigned-clocks = <&cru USB480M>;
169 assigned-clock-parents = <&u2phy>;
170 clock-output-names = "usb480m_phy";
173 u2phy_host: host-port {
174 #phy-cells = <0>;
176 interrupt-names = "linestate";
180 u2phy_otg: otg-port {
181 #phy-cells = <0>;
185 interrupt-names = "otg-bvalid", "otg-id",
193 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd";
195 #address-cells = <1>;
196 #size-cells = <1>;
198 pmu_io_domains: io-domains {
199 compatible = "rockchip,rk1808-pmu-io-voltage-domain";
205 compatible = "arm,psci-1.0";
255 compatible = "mmio-sram";
257 #address-cells = <1>;
258 #size-cells = <1>;
261 ddr-sram@0 {
265 vad_sram: vad-sram@1c0000 {
270 gic: interrupt-controller@ff100000 {
271 compatible = "arm,gic-v3";
272 #interrupt-cells = <3>;
273 #address-cells = <2>;
274 #size-cells = <2>;
276 interrupt-controller;
284 its: interrupt-controller@ff120000 {
285 compatible = "arm,gic-v3-its";
286 msi-controller;
291 cru: clock-controller@ff350000 {
292 compatible = "rockchip,rk1808-cru";
295 #clock-cells = <1>;
296 #reset-cells = <1>;
298 assigned-clocks =
304 assigned-clock-rates =
312 mipi_dphy: mipi-dphy@ff370000 {
313 compatible = "rockchip,rk1808-mipi-dphy";
316 clock-names = "ref", "pclk";
317 clock-output-names = "mipi_dphy_pll";
318 #clock-cells = <0>;
320 reset-names = "apb";
321 #phy-cells = <0>;
327 compatible = "rockchip,rk1808-tsadc";
332 clock-names = "tsadc", "apb_pclk";
333 assigned-clocks = <&cru SCLK_TSADC>;
334 assigned-clock-rates = <50000>;
336 reset-names = "tsadc-apb";
337 #thermal-sensor-cells = <1>;
338 rockchip,hw-tshut-temp = <120000>;
343 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
345 #pwm-cells = <3>;
346 pinctrl-names = "active";
347 pinctrl-0 = <&pwm0_pin>;
349 clock-names = "pwm", "pclk";
354 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
356 #pwm-cells = <3>;
357 pinctrl-names = "active";
358 pinctrl-0 = <&pwm1_pin>;
360 clock-names = "pwm", "pclk";
365 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
367 #pwm-cells = <3>;
368 pinctrl-names = "active";
369 pinctrl-0 = <&pwm2_pin>;
371 clock-names = "pwm", "pclk";
376 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
378 #pwm-cells = <3>;
379 pinctrl-names = "active";
380 pinctrl-0 = <&pwm3_pin>;
382 clock-names = "pwm", "pclk";
387 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
389 #pwm-cells = <3>;
390 pinctrl-names = "active";
391 pinctrl-0 = <&pwm4_pin>;
393 clock-names = "pwm", "pclk";
398 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
400 #pwm-cells = <3>;
401 pinctrl-names = "active";
402 pinctrl-0 = <&pwm5_pin>;
404 clock-names = "pwm", "pclk";
409 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
411 #pwm-cells = <3>;
412 pinctrl-names = "active";
413 pinctrl-0 = <&pwm6_pin>;
415 clock-names = "pwm", "pclk";
420 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
422 #pwm-cells = <3>;
423 pinctrl-names = "active";
424 pinctrl-0 = <&pwm7_pin>;
426 clock-names = "pwm", "pclk";
430 pmu: power-management@ff3e0000 {
431 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd";
434 power: power-controller {
435 compatible = "rockchip,rk1808-power-controller";
436 #power-domain-cells = <1>;
437 #address-cells = <1>;
438 #size-cells = <0>;
495 compatible = "rockchip,rk3399-i2c";
498 clock-names = "i2c", "pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&i2c0_xfer>;
502 #address-cells = <1>;
503 #size-cells = <0>;
512 clock-names = "apb_pclk";
513 #dma-cells = <1>;
514 peripherals-req-type-burst;
518 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
522 clock-names = "baudclk", "apb_pclk";
523 reg-shift = <2>;
524 reg-io-width = <4>;
526 dma-names = "tx", "rx";
527 pinctrl-names = "default";
528 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
533 compatible = "rockchip,rk3399-i2c";
536 clock-names = "i2c", "pclk";
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c1_xfer>;
540 #address-cells = <1>;
541 #size-cells = <0>;
546 compatible = "rockchip,rk3399-i2c";
549 clock-names = "i2c", "pclk";
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c2m0_xfer>;
553 #address-cells = <1>;
554 #size-cells = <0>;
559 compatible = "rockchip,rk3399-i2c";
562 clock-names = "i2c", "pclk";
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c3_xfer>;
566 #address-cells = <1>;
567 #size-cells = <0>;
572 compatible = "rockchip,rk3399-i2c";
575 clock-names = "i2c", "pclk";
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c4_xfer>;
579 #address-cells = <1>;
580 #size-cells = <0>;
585 compatible = "rockchip,rk3399-i2c";
588 clock-names = "i2c", "pclk";
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c5_xfer>;
592 #address-cells = <1>;
593 #size-cells = <0>;
598 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
601 #address-cells = <1>;
602 #size-cells = <0>;
604 clock-names = "spiclk", "apb_pclk";
606 dma-names = "tx", "rx";
607 pinctrl-names = "default", "high_speed";
608 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
609 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>;
614 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
617 #address-cells = <1>;
618 #size-cells = <0>;
620 clock-names = "spiclk", "apb_pclk";
622 dma-names = "tx", "rx";
623 pinctrl-names = "default", "high_speed";
624 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
625 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>;
630 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
634 clock-names = "baudclk", "apb_pclk";
635 reg-shift = <2>;
636 reg-io-width = <4>;
638 dma-names = "tx", "rx";
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>;
645 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
649 clock-names = "baudclk", "apb_pclk";
650 reg-shift = <2>;
651 reg-io-width = <4>;
653 dma-names = "tx", "rx";
654 pinctrl-names = "default";
655 pinctrl-0 = <&uart2m0_xfer>;
660 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
664 clock-names = "baudclk", "apb_pclk";
665 reg-shift = <2>;
666 reg-io-width = <4>;
668 dma-names = "tx", "rx";
669 pinctrl-names = "default";
670 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>;
675 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
679 clock-names = "baudclk", "apb_pclk";
680 reg-shift = <2>;
681 reg-io-width = <4>;
683 dma-names = "tx", "rx";
684 pinctrl-names = "default";
685 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
690 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
693 #address-cells = <1>;
694 #size-cells = <0>;
696 clock-names = "spiclk", "apb_pclk";
698 dma-names = "tx", "rx";
699 pinctrl-names = "default", "high_speed";
700 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>;
701 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>;
706 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
710 clock-names = "baudclk", "apb_pclk";
711 reg-shift = <2>;
712 reg-io-width = <4>;
714 dma-names = "tx", "rx";
715 pinctrl-names = "default";
716 pinctrl-0 = <&uart5_xfer>;
721 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
725 clock-names = "baudclk", "apb_pclk";
726 reg-shift = <2>;
727 reg-io-width = <4>;
729 dma-names = "tx", "rx";
730 pinctrl-names = "default";
731 pinctrl-0 = <&uart6_xfer>;
736 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
740 clock-names = "baudclk", "apb_pclk";
741 reg-shift = <2>;
742 reg-io-width = <4>;
744 dma-names = "tx", "rx";
745 pinctrl-names = "default";
746 pinctrl-0 = <&uart7_xfer>;
751 compatible = "rockchip,rk1808-vop-lit";
753 reg-names = "regs";
757 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
758 power-domains = <&power RK1808_PD_VIO>;
763 #address-cells = <1>;
764 #size-cells = <0>;
768 remote-endpoint = <&dsi_in_vop_lite>;
773 remote-endpoint = <&rgb_in_vop_lite>;
782 interrupt-names = "vopl_mmu";
784 clock-names = "aclk", "hclk";
785 power-domains = <&power RK1808_PD_VIO>;
786 #iommu-cells = <0>;
791 compatible = "rockchip,rk1808-vop-raw";
793 reg-names = "regs";
797 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
798 power-domains = <&power RK1808_PD_VIO>;
803 #address-cells = <1>;
804 #size-cells = <0>;
808 remote-endpoint = <&csi_in_vop_raw>;
817 interrupt-names = "vopr_mmu";
819 clock-names = "aclk", "hclk";
820 power-domains = <&power RK1808_PD_VIO>;
821 #iommu-cells = <0>;
826 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
828 #pwm-cells = <3>;
829 pinctrl-names = "active";
830 pinctrl-0 = <&pwm8_pin>;
832 clock-names = "pwm", "pclk";
837 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
839 #pwm-cells = <3>;
840 pinctrl-names = "active";
841 pinctrl-0 = <&pwm9_pin>;
843 clock-names = "pwm", "pclk";
848 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
850 #pwm-cells = <3>;
851 pinctrl-names = "active";
852 pinctrl-0 = <&pwm10_pin>;
854 clock-names = "pwm", "pclk";
859 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
861 #pwm-cells = <3>;
862 pinctrl-names = "active";
863 pinctrl-0 = <&pwm11_pin>;
865 clock-names = "pwm", "pclk";
870 compatible = "rockchip,rk1808-crypto";
872 clock-names = "sclk_crypto", "sclk_crypto_apk";
874 clock-frequency = <200000000>, <300000000>;
879 compatible = "rockchip,rk1808-i2s-tdm";
883 clock-names = "mclk_tx", "mclk_rx", "hclk";
885 dma-names = "tx", "rx";
887 reset-names = "tx-m", "rx-m";
889 pinctrl-names = "default";
890 pinctrl-0 = <&i2s0_8ch_sclktx
907 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s";
911 clock-names = "i2s_clk", "i2s_hclk";
913 dma-names = "tx", "rx";
914 pinctrl-names = "default";
915 pinctrl-0 = <&i2s1_2ch_sclk
923 compatible = "rockchip,rk1808-pdm", "rockchip,pdm";
926 clock-names = "pdm_clk", "pdm_hclk";
928 dma-names = "rx";
930 reset-names = "pdm-m";
931 pinctrl-names = "default";
932 pinctrl-0 = <&pdm_clk
942 compatible = "rockchip,rk1808-vad";
944 reg-names = "vad";
946 clock-names = "hclk";
948 rockchip,audio-sram = <&vad_sram>;
949 rockchip,audio-src = <0>;
950 rockchip,det-channel = <0>;
956 compatible = "rockchip,rk1808-mipi-csi";
958 reg-names = "csi_regs";
961 clock-names = "pclk", "hs_clk";
963 reset-names = "apb";
965 phy-names = "mipi_dphy";
966 power-domains = <&power RK1808_PD_VIO>;
971 #address-cells = <1>;
972 #size-cells = <0>;
976 remote-endpoint = <&vop_raw_out_csi>;
983 compatible = "rockchip,rk1808-mipi-dsi";
987 clock-names = "pclk", "hs_clk";
989 reset-names = "apb";
991 phy-names = "mipi_dphy";
992 power-domains = <&power RK1808_PD_VIO>;
994 #address-cells = <1>;
995 #size-cells = <0>;
1001 remote-endpoint = <&vop_lite_out_dsi>;
1007 sfc: sfc@ffc50000 { label
1008 compatible = "rockchip,rksfc","rockchip,sfc";
1012 clock-names = "clk_sfc", "hclk_sfc";
1017 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc";
1021 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1022 max-frequency = <150000000>;
1023 fifo-depth = <0x100>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
1034 clock-names = "sclk_npu", "hclk_npu";
1040 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc";
1043 #io-channel-cells = <1>;
1045 clock-names = "saradc", "apb_pclk";
1047 reset-names = "saradc-apb";
1052 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc";
1056 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1057 max-frequency = <150000000>;
1058 fifo-depth = <0x100>;
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>;
1066 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc";
1070 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1071 max-frequency = <150000000>;
1072 fifo-depth = <0x100>;
1078 compatible = "generic-ehci";
1083 clock-names = "usbhost", "arbiter", "utmi";
1085 phy-names = "usb";
1090 compatible = "generic-ohci";
1095 clock-names = "usbhost", "arbiter", "utmi";
1097 phy-names = "usb";
1102 compatible = "rockchip,rk1808-gmac";
1106 interrupt-names = "macirq";
1111 clock-names = "stmmaceth", "mac_clk_rx",
1115 phy-mode = "rgmii";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&rgmii_pins>;
1119 reset-names = "stmmaceth";
1120 /* power-domains = <&power RK1808_PD_GMAC>; */
1125 compatible = "rockchip,rk1808-pinctrl";
1128 #address-cells = <2>;
1129 #size-cells = <2>;
1133 compatible = "rockchip,gpio-bank";
1137 gpio-controller;
1138 #gpio-cells = <2>;
1140 interrupt-controller;
1141 #interrupt-cells = <2>;
1145 compatible = "rockchip,gpio-bank";
1149 gpio-controller;
1150 #gpio-cells = <2>;
1152 interrupt-controller;
1153 #interrupt-cells = <2>;
1157 compatible = "rockchip,gpio-bank";
1161 gpio-controller;
1162 #gpio-cells = <2>;
1164 interrupt-controller;
1165 #interrupt-cells = <2>;
1169 compatible = "rockchip,gpio-bank";
1173 gpio-controller;
1174 #gpio-cells = <2>;
1176 interrupt-controller;
1177 #interrupt-cells = <2>;
1181 compatible = "rockchip,gpio-bank";
1185 gpio-controller;
1186 #gpio-cells = <2>;
1188 interrupt-controller;
1189 #interrupt-cells = <2>;
1192 pcfg_pull_up: pcfg-pull-up {
1193 bias-pull-up;
1196 pcfg_pull_down: pcfg-pull-down {
1197 bias-pull-down;
1200 pcfg_pull_none: pcfg-pull-none {
1201 bias-disable;
1204 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1205 bias-disable;
1206 drive-strength = <2>;
1209 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1210 bias-pull-up;
1211 drive-strength = <2>;
1214 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1215 bias-pull-up;
1216 drive-strength = <4>;
1219 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1220 bias-disable;
1221 drive-strength = <4>;
1224 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1225 bias-pull-down;
1226 drive-strength = <4>;
1229 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1230 bias-disable;
1231 drive-strength = <8>;
1234 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1235 bias-pull-up;
1236 drive-strength = <8>;
1239 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1240 bias-disable;
1241 drive-strength = <12>;
1244 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1245 bias-pull-up;
1246 drive-strength = <12>;
1249 pcfg_pull_none_smt: pcfg-pull-none-smt {
1250 bias-disable;
1251 input-schmitt-enable;
1254 pcfg_output_high: pcfg-output-high {
1255 output-high;
1258 pcfg_output_low: pcfg-output-low {
1259 output-low;
1262 pcfg_input_high: pcfg-input-high {
1263 bias-pull-up;
1264 input-enable;
1267 pcfg_input: pcfg-input {
1268 input-enable;
1272 emmc_clk: emmc-clk {
1278 emmc_rstnout: emmc-rstnout {
1284 emmc_bus8: emmc-bus8 {
1304 emmc_pwren: emmc-pwren {
1309 emmc_cmd: emmc-cmd {
1316 rgmii_pins: rgmii-pins {
1350 rmii_pins: rmii-pins {
1376 i2c0_xfer: i2c0-xfer {
1386 i2c1_xfer: i2c1-xfer {
1396 i2c2m0_xfer: i2c2m0-xfer {
1406 i2c3_xfer: i2c3-xfer {
1416 i2c4_xfer: i2c4-xfer {
1426 i2c5_xfer: i2c5-xfer {
1436 i2s1_2ch_lrck: i2s1-2ch-lrck {
1440 i2s1_2ch_sclk: i2s1-2ch-sclk {
1444 i2s1_2ch_mclk: i2s1-2ch-mclk {
1448 i2s1_2ch_sdo: i2s1-2ch-sdo {
1452 i2s1_2ch_sdi: i2s1-2ch-sdi {
1459 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1463 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1467 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1471 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1475 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1479 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1483 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1487 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1491 i2s0_8ch_mclk: i2s0-8ch-mclk {
1495 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1499 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1503 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1507 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1514 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1520 lcdc_rgb_den_pin: lcdc-rgb-den-pin {
1526 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1532 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1538 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin {
1544 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin {
1550 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins {
1590 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins {
1628 pciusb_pins: pciusb-pins {
1650 pdm_clk: pdm-clk {
1656 pdm_sdi3: pdm-sdi3 {
1661 pdm_sdi2: pdm-sdi2 {
1666 pdm_sdi1: pdm-sdi1 {
1671 pdm_clk1: pdm-clk1 {
1676 pdm_sdi0: pdm-sdi0 {
1683 pwm0_pin: pwm0-pin {
1690 pwm1_pin: pwm1-pin {
1697 pwm2_pin: pwm2-pin {
1704 pwm3_pin: pwm3-pin {
1711 pwm4_pin: pwm4-pin {
1718 pwm5_pin: pwm5-pin {
1724 pwm6_pin: pwm6-pin {
1731 pwm7_pin: pwm7-pin {
1738 pwm8_pin: pwm8-pin {
1745 pwm9_pin: pwm9-pin {
1752 pwm10_pin: pwm10-pin {
1759 pwm11_pin: pwm11-pin {
1766 sdmmc0_bus4: sdmmc0-bus4 {
1777 sdmmc0_cmd: sdmmc0-cmd {
1781 sdmmc0_clk: sdmmc0-clk {
1788 sdmmc1_bus4: sdmmc1-bus4 {
1800 sdmmc1_cmd: sdmmc1-cmd {
1805 sdmmc1_clk: sdmmc1-clk {
1812 spi0_mosi: spi0-mosi {
1817 spi0_miso: spi0-miso {
1822 spi0_csn: spi0-csn {
1827 spi0_clk: spi0-clk {
1832 spi0_mosi_hs: spi0-mosi-hs {
1837 spi0_miso_hs: spi0-miso-hs {
1842 spi0_csn_hs: spi0-csn-hs {
1847 spi0_clk_hs: spi0-clk-hs {
1854 spi1_clk: spi1-clk {
1859 spi1_mosi: spi1-mosi {
1864 spi1_csn0: spi1-csn0 {
1869 spi1_miso: spi1-miso {
1874 spi1_csn1: spi1-csn1 {
1879 spi1_clk_hs: spi1-clk-hs {
1884 spi1_mosi_hs: spi1-mosi-hs {
1889 spi1_csn0_hs: spi1-csn0-hs {
1894 spi1_miso_hs: spi1-miso-hs {
1899 spi1_csn1_hs: spi1-csn1-hs {
1906 spi1m1_clk: spi1m1-clk {
1911 spi1m1_mosi: spi1m1-mosi {
1916 spi1m1_csn0: spi1m1-csn0 {
1921 spi1m1_miso: spi1m1-miso {
1926 spi1m1_csn1: spi1m1-csn1 {
1931 spi1m1_clk_hs: spi1m1-clk-hs {
1936 spi1m1_mosi_hs: spi1m1-mosi-hs {
1941 spi1m1_csn0_hs: spi1m1-csn0-hs {
1946 spi1m1_miso_hs: spi1m1-miso-hs {
1951 spi1m1_csn1_hs: spi1m1-csn1-hs {
1958 spi2m0_miso: spi2m0-miso {
1963 spi2m0_clk: spi2m0-clk {
1968 spi2m0_mosi: spi2m0-mosi {
1973 spi2m0_csn: spi2m0-csn {
1978 spi2m0_miso_hs: spi2m0-miso-hs {
1983 spi2m0_clk_hs: spi2m0-clk-hs {
1988 spi2m0_mosi_hs: spi2m0-mosi-hs {
1993 spi2m0_csn_hs: spi2m0-csn-hs {
2000 spi2m1_miso: spi2m1-miso {
2005 spi2m1_clk: spi2m1-clk {
2010 spi2m1_mosi: spi2m1-mosi {
2015 spi2m1_csn: spi2m1-csn {
2020 spi2m1_miso_hs: spi2m1-miso-hs {
2025 spi2m1_clk_hs: spi2m1-clk-hs {
2030 spi2m1_mosi_hs: spi2m1-mosi-hs {
2035 spi2m1_csn_hs: spi2m1-csn-hs {
2042 uart0_xfer: uart0-xfer {
2050 uart0_cts: uart0-cts {
2055 uart0_rts: uart0-rts {
2062 uart1m0_xfer: uart1m0-xfer {
2070 uart1m1_xfer: uart1m1-xfer {
2078 uart1_cts: uart1-cts {
2083 uart1_rts: uart1-rts {
2090 uart2m0_xfer: uart2m0-xfer {
2098 uart2m1_xfer: uart2m1-xfer {
2106 uart2m2_xfer: uart2m2-xfer {
2116 uart3m0_xfer: uart3m0-xfer {
2124 uart3_ctsm0: uart3-ctsm0 {
2129 uart3_rtsm0: uart3-rtsm0 {
2136 uart4_xfer: uart4-xfer {
2144 uart4_cts: uart4-cts {
2149 uart4_rts: uart4-rts {
2156 uart5_xfer: uart5-xfer {
2166 uart6_xfer: uart6-xfer {
2176 uart7_xfer: uart7-xfer {
2186 tsadc_otp_gpio: tsadc-otp-gpio {
2191 tsadc_otp_out: tsadc-otp-out {