Lines Matching +full:sclk +full:- +full:strength
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/px30-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/px30-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
33 #address-cells = <2>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a35", "arm,armv8";
40 enable-method = "psci";
45 compatible = "arm,cortex-a35", "arm,armv8";
47 enable-method = "psci";
51 compatible = "arm,cortex-a35", "arm,armv8";
53 enable-method = "psci";
57 compatible = "arm,cortex-a35", "arm,armv8";
59 enable-method = "psci";
63 arm-pmu {
64 compatible = "arm,cortex-a53-pmu";
69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
73 compatible = "rockchip,px30-dmc", "syscon";
77 display_subsystem: display-subsystem {
78 compatible = "rockchip,display-subsystem";
85 compatible = "linaro,optee-tz";
90 gmac_clkin: external-gmac-clock {
91 compatible = "fixed-clock";
92 clock-frequency = <50000000>;
93 clock-output-names = "gmac_clkin";
94 #clock-cells = <0>;
98 compatible = "arm,psci-1.0";
103 compatible = "arm,armv8-timer";
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <24000000>;
114 clock-output-names = "xin24m";
117 pmu: power-management@ff000000 {
118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
121 power: power-controller {
122 compatible = "rockchip,px30-power-controller";
123 #power-domain-cells = <1>;
124 #address-cells = <1>;
125 #size-cells = <0>;
194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
196 #address-cells = <1>;
197 #size-cells = <1>;
199 pmu_io_domains: io-domains {
200 compatible = "rockchip,px30-pmu-io-voltage-domain";
204 reboot-mode {
205 compatible = "syscon-reboot-mode";
207 mode-bootloader = <BOOT_BL_DOWNLOAD>;
208 mode-charge = <BOOT_CHARGING>;
209 mode-fastboot = <BOOT_FASTBOOT>;
210 mode-loader = <BOOT_BL_DOWNLOAD>;
211 mode-normal = <BOOT_NORMAL>;
212 mode-recovery = <BOOT_RECOVERY>;
213 mode-ums = <BOOT_UMS>;
216 pmu_pvtm: pmu-pvtm {
217 compatible = "rockchip,px30-pmu-pvtm";
219 clock-names = "pmu";
225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
229 clock-names = "baudclk", "apb_pclk";
230 reg-shift = <2>;
231 reg-io-width = <4>;
233 #dma-cells = <2>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
244 clock-names = "i2s_clk", "i2s_hclk";
246 dma-names = "tx", "rx";
251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
255 clock-names = "i2s_clk", "i2s_hclk";
257 dma-names = "tx", "rx";
262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
266 clock-names = "i2s_clk", "i2s_hclk";
268 dma-names = "tx", "rx";
276 clock-names = "pdm_clk", "pdm_hclk";
278 dma-names = "rx";
283 compatible = "rockchip,px30-crypto";
285 clock-names = "sclk_crypto", "apkclk_crypto";
287 clock-frequency = <200000000>, <300000000>;
291 gic: interrupt-controller@ff131000 {
292 compatible = "arm,gic-400";
293 #interrupt-cells = <3>;
294 #address-cells = <0>;
295 interrupt-controller;
305 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
307 #address-cells = <1>;
308 #size-cells = <1>;
310 io_domains: io-domains {
311 compatible = "rockchip,px30-io-voltage-domain";
316 compatible = "rockchip,px30-lvds";
318 phy-names = "phy";
322 #address-cells = <1>;
323 #size-cells = <0>;
327 #address-cells = <1>;
328 #size-cells = <0>;
332 remote-endpoint = <&vopb_out_lvds>;
337 remote-endpoint = <&vopl_out_lvds>;
344 compatible = "rockchip,px30-rgb";
345 pinctrl-names = "default", "sleep";
346 pinctrl-0 = <&lcdc_m0_rgb_pins>;
347 pinctrl-1 = <&lcdc_m0_sleep_pins>;
351 #address-cells = <1>;
352 #size-cells = <0>;
356 #address-cells = <1>;
357 #size-cells = <0>;
361 remote-endpoint = <&vopb_out_rgb>;
366 remote-endpoint = <&vopl_out_rgb>;
374 compatible = "syscon", "simple-mfd";
376 #address-cells = <1>;
377 #size-cells = <1>;
380 compatible = "rockchip,px30-pvtm";
382 clock-names = "core";
388 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
392 clock-names = "sclk_uart", "pclk_uart";
393 reg-shift = <2>;
394 reg-io-width = <4>;
396 #dma-cells = <2>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
403 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
407 clock-names = "baudclk", "apb_pclk";
408 reg-shift = <2>;
409 reg-io-width = <4>;
411 #dma-cells = <2>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart2m0_xfer>;
418 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
422 clock-names = "baudclk", "apb_pclk";
423 reg-shift = <2>;
424 reg-io-width = <4>;
426 #dma-cells = <2>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
433 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
437 clock-names = "baudclk", "apb_pclk";
438 reg-shift = <2>;
439 reg-io-width = <4>;
441 #dma-cells = <2>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
448 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
452 clock-names = "baudclk", "apb_pclk";
453 reg-shift = <2>;
454 reg-io-width = <4>;
456 #dma-cells = <2>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
463 compatible = "rockchip,rk3399-i2c";
466 clock-names = "i2c", "pclk";
468 pinctrl-names = "default";
469 pinctrl-0 = <&i2c0_xfer>;
470 #address-cells = <1>;
471 #size-cells = <0>;
476 compatible = "rockchip,rk3399-i2c";
479 clock-names = "i2c", "pclk";
481 pinctrl-names = "default";
482 pinctrl-0 = <&i2c1_xfer>;
483 #address-cells = <1>;
484 #size-cells = <0>;
489 compatible = "rockchip,rk3399-i2c";
492 clock-names = "i2c", "pclk";
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c2_xfer>;
496 #address-cells = <1>;
497 #size-cells = <0>;
502 compatible = "rockchip,rk3399-i2c";
505 clock-names = "i2c", "pclk";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c3_xfer>;
509 #address-cells = <1>;
510 #size-cells = <0>;
515 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
518 #address-cells = <1>;
519 #size-cells = <0>;
521 clock-names = "spiclk", "apb_pclk";
523 #dma-cells = <2>;
524 dma-names = "tx", "rx";
525 pinctrl-names = "default";
526 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
531 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
534 #address-cells = <1>;
535 #size-cells = <0>;
537 clock-names = "spiclk", "apb_pclk";
539 #dma-cells = <2>;
540 dma-names = "tx", "rx";
541 pinctrl-names = "default";
542 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>;
547 compatible = "snps,dw-wdt";
554 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
556 #pwm-cells = <3>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm0_pin>;
560 clock-names = "pwm", "pclk";
565 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
567 #pwm-cells = <3>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pwm1_pin>;
571 clock-names = "pwm", "pclk";
576 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
578 #pwm-cells = <3>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&pwm2_pin>;
582 clock-names = "pwm", "pclk";
587 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
589 #pwm-cells = <3>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>;
593 clock-names = "pwm", "pclk";
598 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
600 #pwm-cells = <3>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&pwm4_pin>;
604 clock-names = "pwm", "pclk";
609 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
611 #pwm-cells = <3>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&pwm5_pin>;
615 clock-names = "pwm", "pclk";
620 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
622 #pwm-cells = <3>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pwm6_pin>;
626 clock-names = "pwm", "pclk";
631 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
633 #pwm-cells = <3>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&pwm7_pin>;
637 clock-names = "pwm", "pclk";
642 compatible = "simple-bus";
643 #address-cells = <2>;
644 #size-cells = <2>;
653 clock-names = "apb_pclk";
654 #dma-cells = <1>;
655 peripherals-req-type-burst;
660 compatible = "rockchip,px30-tsadc";
665 clock-names = "tsadc", "apb_pclk";
666 assigned-clocks = <&cru SCLK_TSADC>;
667 assigned-clock-rates = <50000>;
669 reset-names = "tsadc-apb";
670 pinctrl-names = "init", "default", "sleep";
671 pinctrl-0 = <&tsadc_otp_gpio>;
672 pinctrl-1 = <&tsadc_otp_out>;
673 pinctrl-2 = <&tsadc_otp_gpio>;
674 #thermal-sensor-cells = <1>;
675 rockchip,hw-tshut-temp = <100000>;
680 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
683 #io-channel-cells = <1>;
685 clock-names = "saradc", "apb_pclk";
687 reset-names = "saradc-apb";
691 cru: clock-controller@ff2b0000 {
692 compatible = "rockchip,px30-cru";
695 #clock-cells = <1>;
696 #reset-cells = <1>;
698 assigned-clocks =
702 assigned-clock-rates =
708 pmucru: pmu-clock-controller@ff2bc000 {
709 compatible = "rockchip,px30-pmucru";
712 #clock-cells = <1>;
713 #reset-cells = <1>;
715 assigned-clocks =
720 assigned-clock-rates =
728 compatible = "rockchip,px30-usb2phy-grf", "syscon",
729 "simple-mfd";
731 #address-cells = <1>;
732 #size-cells = <1>;
734 u2phy: usb2-phy@100 {
735 compatible = "rockchip,px30-usb2phy",
736 "rockchip,rk3328-usb2phy";
739 clock-names = "phyclk";
740 #clock-cells = <0>;
741 assigned-clocks = <&cru USB480M>;
742 assigned-clock-parents = <&u2phy>;
743 clock-output-names = "usb480m_phy";
746 u2phy_host: host-port {
747 #phy-cells = <0>;
749 interrupt-names = "linestate";
753 u2phy_otg: otg-port {
754 #phy-cells = <0>;
758 interrupt-names = "otg-bvalid", "otg-id",
765 video_phy: video-phy@ff2e0000 {
766 compatible = "rockchip,px30-video-phy";
771 clock-names = "ref", "pclk_phy", "pclk_host";
772 #clock-cells = <0>;
774 reset-names = "rst";
775 power-domains = <&power PX30_PD_VO>;
776 #phy-cells = <0>;
781 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
786 clock-names = "otg";
788 g-np-tx-fifo-size = <16>;
789 g-rx-fifo-size = <275>;
790 g-tx-fifo-size = <256 128 128 64 64 32>;
791 g-use-dma;
793 phy-names = "usb2-phy";
798 compatible = "generic-ehci";
803 clock-names = "usbhost", "arbiter", "utmi";
805 phy-names = "usb";
810 compatible = "generic-ohci";
815 clock-names = "usbhost", "arbiter", "utmi";
817 phy-names = "usb";
821 compatible = "rockchip,px30-gmac";
825 interrupt-names = "macirq";
830 clock-names = "stmmaceth", "mac_clk_rx",
834 phy-mode = "rmii";
835 pinctrl-names = "default";
836 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
838 reset-names = "stmmaceth";
839 power-domains = <&power PX30_PD_GMAC>;
844 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
846 max-frequency = <150000000>;
849 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
850 fifo-depth = <0x100>;
851 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
853 pinctrl-names = "default";
854 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
859 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
861 max-frequency = <150000000>;
864 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
865 fifo-depth = <0x100>;
871 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
873 max-frequency = <150000000>;
876 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
877 fifo-depth = <0x100>;
887 clock-names = "clk_sfc", "hclk_sfc";
892 compatible = "rockchip,rk-nandc";
897 clock-names = "clk_nandc", "hclk_nandc";
902 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
908 interrupt-names = "GPU", "MMU", "JOB";
911 clock-names = "clk_mali";
921 interrupt-names = "irq_dec";
934 interrupt-names = "irq_enc", "irq_dec";
947 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
951 reset-names = "video_a", "video_h", "niu_a", "niu_h",
963 interrupt-names = "hevc_mmu";
965 clock-names = "aclk", "hclk";
966 #iommu-cells = <0>;
973 interrupt-names = "vpu_mmu";
975 clock-names = "aclk", "hclk";
976 #iommu-cells = <0>;
980 compatible = "rockchip,px30-mipi-dsi";
984 clock-names = "pclk", "hs_clk";
986 reset-names = "apb";
988 phy-names = "mipi_dphy";
989 power-domains = <&power PX30_PD_VO>;
991 #address-cells = <1>;
992 #size-cells = <0>;
996 #address-cells = <1>;
997 #size-cells = <0>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1006 remote-endpoint = <&vopl_out_dsi>;
1011 remote-endpoint = <&vopb_out_dsi>;
1018 compatible = "rockchip,px30-vop-big";
1020 reg-names = "regs", "gamma_lut";
1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1034 remote-endpoint = <&lvds_in_vopb>;
1039 remote-endpoint = <&dsi_in_vopb>;
1044 remote-endpoint = <&rgb_in_vopb>;
1053 interrupt-names = "vopb_mmu";
1055 clock-names = "aclk", "hclk";
1056 #iommu-cells = <0>;
1061 compatible = "rockchip,px30-vop-lit";
1063 reg-names = "regs", "gamma_lut";
1067 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1077 remote-endpoint = <&lvds_in_vopl>;
1082 remote-endpoint = <&dsi_in_vopl>;
1087 remote-endpoint = <&rgb_in_vopl>;
1096 interrupt-names = "vopl_mmu";
1098 clock-names = "aclk", "hclk";
1099 #iommu-cells = <0>;
1109 clock-names = "aclk_rga", "hclk_rga";
1110 dma-coherent;
1119 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out";
1121 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
1122 pinctrl-names = "cif_pin_all";
1123 pinctrl-0 = <&dvp_d2d9_m0>;
1131 interrupt-names = "vip_mmu";
1133 clock-names = "aclk", "hclk";
1135 #iommu-cells = <0>;
1140 compatible = "rockchip,px30-isp", "rockchip,isp";
1145 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe",
1148 reset-names = "rst_isp", "rst_mipicsiphy";
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&cif_clkout_m0>;
1155 rockchip,isp,iommu-enable = <1>;
1164 interrupt-names = "isp_mmu";
1166 clock-names = "aclk", "hclk";
1168 #iommu-cells = <0>;
1273 compatible = "rockchip,px30-pinctrl";
1276 #address-cells = <2>;
1277 #size-cells = <2>;
1281 compatible = "rockchip,gpio-bank";
1285 gpio-controller;
1286 #gpio-cells = <2>;
1288 interrupt-controller;
1289 #interrupt-cells = <2>;
1293 compatible = "rockchip,gpio-bank";
1297 gpio-controller;
1298 #gpio-cells = <2>;
1300 interrupt-controller;
1301 #interrupt-cells = <2>;
1305 compatible = "rockchip,gpio-bank";
1309 gpio-controller;
1310 #gpio-cells = <2>;
1312 interrupt-controller;
1313 #interrupt-cells = <2>;
1317 compatible = "rockchip,gpio-bank";
1321 gpio-controller;
1322 #gpio-cells = <2>;
1324 interrupt-controller;
1325 #interrupt-cells = <2>;
1328 pcfg_pull_up: pcfg-pull-up {
1329 bias-pull-up;
1332 pcfg_pull_down: pcfg-pull-down {
1333 bias-pull-down;
1336 pcfg_pull_none: pcfg-pull-none {
1337 bias-disable;
1340 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1341 bias-disable;
1342 drive-strength = <2>;
1345 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1346 bias-pull-up;
1347 drive-strength = <2>;
1350 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1351 bias-pull-up;
1352 drive-strength = <4>;
1355 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1356 bias-disable;
1357 drive-strength = <4>;
1360 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1361 bias-pull-down;
1362 drive-strength = <4>;
1365 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1366 bias-disable;
1367 drive-strength = <8>;
1370 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1371 bias-pull-up;
1372 drive-strength = <8>;
1375 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1376 bias-disable;
1377 drive-strength = <12>;
1380 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1381 bias-pull-up;
1382 drive-strength = <12>;
1385 pcfg_pull_none_smt: pcfg-pull-none-smt {
1386 bias-disable;
1387 input-schmitt-enable;
1390 pcfg_output_high: pcfg-output-high {
1391 output-high;
1394 pcfg_output_low: pcfg-output-low {
1395 output-low;
1398 pcfg_input_high: pcfg-input-high {
1399 bias-pull-up;
1400 input-enable;
1403 pcfg_input: pcfg-input {
1404 input-enable;
1408 i2c0_xfer: i2c0-xfer {
1416 i2c1_xfer: i2c1-xfer {
1424 i2c2_xfer: i2c2-xfer {
1432 i2c3_xfer: i2c3-xfer {
1440 tsadc_otp_gpio: tsadc-otp-gpio {
1445 tsadc_otp_out: tsadc-otp-out {
1452 uart0_xfer: uart0-xfer {
1458 uart0_cts: uart0-cts {
1463 uart0_rts: uart0-rts {
1468 uart0_rts_gpio: uart0-rts-gpio {
1475 uart1_xfer: uart1-xfer {
1481 uart1_cts: uart1-cts {
1486 uart1_rts: uart1-rts {
1491 uart1_rts_gpio: uart1-rts-gpio {
1497 uart2-m0 {
1498 uart2m0_xfer: uart2m0-xfer {
1505 uart2-m1 {
1506 uart2m1_xfer: uart2m1-xfer {
1513 uart3-m0 {
1514 uart3m0_xfer: uart3m0-xfer {
1520 uart3m0_cts: uart3m0-cts {
1525 uart3m0_rts: uart3m0-rts {
1530 uart3m0_rts_gpio: uart3m0-rts-gpio {
1536 uart3-m1 {
1537 uart3m1_xfer: uart3m1-xfer {
1543 uart3m1_cts: uart3m1-cts {
1548 uart3m1_rts: uart3m1-rts {
1553 uart3m1_rts_gpio: uart3m1-rts-gpio {
1561 uart4_xfer: uart4-xfer {
1567 uart4_cts: uart4-cts {
1573 uart4_rts: uart4-rts {
1581 uart5_xfer: uart5-xfer {
1587 uart5_cts: uart5-cts {
1593 uart5_rts: uart5-rts {
1600 spi0_clk: spi0-clk {
1605 spi0_csn: spi0-csn {
1610 spi0_miso: spi0-miso {
1615 spi0_mosi: spi0-mosi {
1622 spi1_clk: spi1-clk {
1627 spi1_csn: spi1-csn {
1632 spi1_miso: spi1-miso {
1637 spi1_mosi: spi1-mosi {
1644 pdm_clk0m0: pdm-clk0m0 {
1649 pdm_clk0m1: pdm-clk0m1 {
1654 pdm_clk1: pdm-clk1 {
1659 pdm_sdi0m0: pdm-sdi0m0 {
1664 pdm_sdi0m1: pdm-sdi0m1 {
1669 pdm_sdi1: pdm-sdi1 {
1674 pdm_sdi2: pdm-sdi2 {
1679 pdm_sdi3: pdm-sdi3 {
1684 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1689 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1694 pdm_clk1_sleep: pdm-clk1-sleep {
1699 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1704 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1709 pdm_sdi1_sleep: pdm-sdi1-sleep {
1714 pdm_sdi2_sleep: pdm-sdi2-sleep {
1719 pdm_sdi3_sleep: pdm-sdi3-sleep {
1726 i2s0_8ch_mclk: i2s0-8ch-mclk {
1731 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1736 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1741 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1746 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1751 i2s0_8ch_sdo: i2s0-8ch-sdo {
1756 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1761 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1766 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1771 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1776 i2s0_8ch_sdi: i2s0-8ch-sdi {
1781 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1786 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1791 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1796 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1803 i2s1_2ch_mclk: i2s1-2ch-mclk {
1808 i2s1_2ch_sclk: i2s1-2ch-sclk {
1813 i2s1_2ch_lrck: i2s1-2ch-lrck {
1818 i2s1_2ch_sdi: i2s1-2ch-sdi {
1823 i2s1_2ch_sdo: i2s1-2ch-sdo {
1830 i2s2_2ch_mclk: i2s2-2ch-mclk {
1835 i2s2_2ch_sclk: i2s2-2ch-sclk {
1840 i2s2_2ch_lrck: i2s2-2ch-lrck {
1845 i2s2_2ch_sdi: i2s2-2ch-sdi {
1850 i2s2_2ch_sdo: i2s2-2ch-sdo {
1857 sdmmc_clk: sdmmc-clk {
1862 sdmmc_cmd: sdmmc-cmd {
1867 sdmmc_det: sdmmc-det {
1872 sdmmc_bus1: sdmmc-bus1 {
1877 sdmmc_bus4: sdmmc-bus4 {
1885 sdmmc_gpio: sdmmc-gpio {
1897 sdio_clk: sdio-clk {
1902 sdio_cmd: sdio-cmd {
1907 sdio_bus4: sdio-bus4 {
1915 sdio_gpio: sdio-gpio {
1927 emmc_clk: emmc-clk {
1932 emmc_cmd: emmc-cmd {
1937 emmc_pwren: emmc-pwren {
1942 emmc_rstnout: emmc-rstnout {
1947 emmc_bus1: emmc-bus1 {
1952 emmc_bus4: emmc-bus4 {
1960 emmc_bus8: emmc-bus8 {
1974 flash_cs0: flash-cs0 {
1979 flash_rdy: flash-rdy {
1984 flash_dqs: flash-dqs {
1989 flash_ale: flash-ale {
1994 flash_cle: flash-cle {
1999 flash_wrn: flash-wrn {
2004 flash_csl: flash-csl {
2009 flash_rdn: flash-rdn {
2014 flash_bus8: flash-bus8 {
2028 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins {
2060 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins {
2094 pwm0_pin: pwm0-pin {
2101 pwm1_pin: pwm1-pin {
2108 pwm2_pin: pwm2-pin {
2115 pwm3_pin: pwm3-pin {
2122 pwm4_pin: pwm4-pin {
2129 pwm5_pin: pwm5-pin {
2136 pwm6_pin: pwm6-pin {
2143 pwm7_pin: pwm7-pin {
2150 rmii_pins: rmii-pins {
2172 mac_refclk_12ma: mac-refclk-12ma {
2177 mac_refclk: mac-refclk {
2183 cif-m0 {
2184 cif_clkout_m0: cif-clkout-m0 {
2188 dvp_d2d9_m0: dvp-d2d9-m0 {
2204 dvp_d0d1_m0: dvp-d0d1-m0 {
2210 dvp_d10d11_m0:d10-d11-m0 {
2217 cif-m1 {
2218 cif_clkout_m1: cif-clkout-m1 {
2222 dvp_d2d9_m1: dvp-d2d9-m1 {
2238 dvp_d0d1_m1: dvp-d0d1-m1 {
2244 dvp_d10d11_m1:d10-d11-m1 {
2252 isp_prelight: isp-prelight {