arm/dts/px30-u-boot.dtsi

4  * SPDX-License-Identifier:     GPL-2.0+
14 		u-boot,spl-boot-order = &emmc, &sdmmc;
15 		stdout-path = &uart2;
18 	secure-otp@ff110000 {
19 		compatible = "rockchip,px30-secure-otp";
27 	u-boot,dm-pre-reloc;
31 	u-boot,dm-pre-reloc;
35 	clock-frequency = <24000000>;
36 	u-boot,dm-pre-reloc;
40 	clock-frequency = <24000000>;
41 	u-boot,dm-pre-reloc;
45 	u-boot,dm-pre-reloc;
50 	u-boot,dm-spl;
54 	u-boot,dm-spl;
58 	u-boot,dm-spl;
62 	u-boot,dm-spl;
66 	u-boot,dm-spl;
70 	u-boot,dm-spl;
74 	u-boot,dm-spl;
79 	u-boot,dm-pre-reloc;
84 	u-boot,dm-pre-reloc;
89 	u-boot,dm-pre-reloc;
94 	u-boot,dm-pre-reloc;
99 	u-boot,dm-pre-reloc;
103 	u-boot,dm-pre-reloc;
108 	u-boot,dm-pre-reloc;
113 	u-boot,dm-pre-reloc;
118 	u-boot,dm-spl;
119 	/delete-property/ pinctrl-names;
120 	/delete-property/ pinctrl-0;
121 	/delete-property/ assigned-clocks;
122 	/delete-property/ assigned-clock-rates;
125 	#address-cells = <1>;
126 	#size-cells = <0>;
128 		u-boot,dm-spl;
129 		compatible = "spi-nand";
131 		spi-tx-bus-width = <1>;
132 		spi-rx-bus-width = <4>;
133 		spi-max-frequency = <75000000>;
137 		u-boot,dm-spl;
138 		compatible = "jedec,spi-nor";
141 		spi-tx-bus-width = <1>;
142 		spi-rx-bus-width = <4>;
143 		spi-max-frequency = <100000000>;
148 	u-boot,dm-pre-reloc;
150 	#address-cells = <1>;
151 	#size-cells = <0>;
153 	nand@0 {
154 		u-boot,dm-pre-reloc;
156 		nand-ecc-mode = "hw_syndrome";
157 		nand-ecc-strength = <16>;
158 		nand-ecc-step-size = <1024>;