soc/codecs/es8396.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * ES8396.h  --  ES8396 ALSA SoC Audio Codec
22 /* Register 0x02 for PLL power down/up, reset, divider and divider dither */
24 /* Register 0x03 for PLL low power mode and PLL power supply selection */
28 /* Register 0x05-0x07 for PLL k cofficient*/
44 /* Register 0x0E for BCLK divider1 in I2S BUS Master mode*/
46 /* Register 0x0F for BCLK divider2 in I2S BUS Master mode*/
48 /* Register 0x10 for LRCK divider3 in I2S BUS Master mode*/
50 /* Register 0x11 for LRCK divider4 in I2S BUS Master mode*/
54 /* Register 0x12 for SDP1 Master or slave mode*/
56 /* Register 0x13 for SDP2 Master or slave mode*/
58 /* Register 0x14 for SDP1 Master or slave mode*/
90 /* Register 0x21 for SDP1 Digital GAIN AND TDM MODE*/
108 /* Register 0x29 for SPK MIXER REFERENCE AND LOW POWER MODE*/
118 /* Register 0x2D for HP MIXER REFERENCE AND LOW POWER MODE*/
128 /* Register 0x31 for AX MIXER REFERENCE AND LOW POWER MODE*/
138 /* Register 0x35 for LN MIXER REFERENCE AND LOW POWER MODE*/
148 /* Register 0x39 for MN MIXER REFERENCE AND LOW POWER MODE*/
178 /* Register 0x45 for MONOHP REFERENCE AND LOW POWER MODE*/
214 /* Register 0x55 for ADC HIGH PASS FILTER,U-LAW/A-LAW COMPMODE,DATA SELECTION*/
234 /* Register 0x5F for ADC LOW POWER MODE AND REFERENCE*/
256 /* Register 0x69 for DAC JACK DETECTION AND U/A-LAW COMPRESS */
266 /* Register 0x6E for DAC REFERENCE AND POWER CONTROL */
273  * SUCH AS ANALOG POWER CONTROL, AVDDLDO POWER CONTROL */
287 /* Write 0XA0 TO REG0X76 to ENABLE TEST MODE*/