Lines Matching +full:enable +full:- +full:charge +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ES8396.h -- ES8396 ALSA SoC Audio Codec
28 /* Register 0x05-0x07 for PLL k cofficient*/
32 /* Register 0x08 for ADC,DAC CHARGE PUMP and CLASS D clock switch*/
38 /* Register 0x0B for CHARGE PUMP CLOCK divider*/
42 /* Register 0x0D for DLL control and DAC MCLK SELECTION*/
60 /* Register 0x15 for ADLRCK or GPIO control*/
152 /* Register 0x3A for CLASS D control and SOURCE SELECTION*/
154 /* Register 0x3B for CLASS D Enabled and Volume Control*/
156 /* Register 0x3C for CLASS D CONTROL */
158 /* Register 0x3D for CLASS D CONTROL*/
166 /* Register 0x40 for CPHP ENABLE */
168 /* Register 0x41 for CPHP VOLUME AND ICAL ENABLE*/
170 /* Register 0x42 for CPHP CONTROL */
172 /* Register 0x43 for CPHP CONTROL*/
174 /* Register 0x44 for CPHP CONTROL*/
184 /* Register 0x48 for MONOHP P BOOST AND MUTE CONTROL*/
186 /* Register 0x49 for MONOHP N BOOST AND MUTE CONTROL */
190 /* Register 0x4A for LNOUT LOUT1 ENABLE AND MIXER*/
192 /* Register 0x4B for LNOUT ROUT1 ENABLE AND MIXER*/
194 /* Register 0x4C for LNOUT LOUT2 ENABLE AND MIXER*/
196 /* Register 0x4D for LNOUT ROUT2 ENABLE AND MIXER*/
198 /* Register 0x4E for LNOUT LOUT1 GAIN CONTROL */
200 /* Register 0x4F for LNOUT ROUT1 GAIN CONTROL */
202 /* Register 0x50 for LNOUT LOUT2 GAIN CONTROL */
204 /* Register 0x51 for LNOUT ROUT2 GAIN CONTROL */
210 /* Register 0x53 for ADC CHIP STATE MACHINE and Digital Control*/
214 /* Register 0x55 for ADC HIGH PASS FILTER,U-LAW/A-LAW COMPMODE,DATA SELECTION*/
220 /* Register 0x58 for ADC ALC CONTROL 1*/
222 /* Register 0x59 for ADC ALC CONTROL 2 */
224 /* Register 0x5A for ADC ALC CONTROL 3 */
226 /* Register 0x5B for ADC ALC CONTROL 4 */
228 /* Register 0x5C for ADC ALC CONTROL 5*/
230 /* Register 0x5D for ADC ALC CONTROL 6*/
232 /* Register 0x5E for ADC ANALOG CONTROL*/
250 /* Register 0x66 for DAC CHIP STATE MACHINE AND MUTE CONTROL*/
252 /* Register 0x67 for DAC RAMPE RATE AND MONO/ZERO CONTROL*/
256 /* Register 0x69 for DAC JACK DETECTION AND U/A-LAW COMPRESS */
262 /* Register 0x6C for DAC LIMITER CONTROL 1 */
264 /* Register 0x6D for DAC LIMITER CONTROL 2 */
266 /* Register 0x6E for DAC REFERENCE AND POWER CONTROL */
272 /* Register 0x70 for CHIP ANALOG CONTROL,
273 * SUCH AS ANALOG POWER CONTROL, AVDDLDO POWER CONTROL */
281 /* Register 0x74 for MICBIAS CONTROL */
283 /* Register 0x75 for MIC ENABLE AND IBIASGEN SELECTION*/
287 /* Write 0XA0 TO REG0X76 to ENABLE TEST MODE*/