Lines Matching refs:mem_base
1114 void __iomem *mem_base; member
3532 writew(gpio_data, spec->mem_base + 0x320); in ca0113_mmio_gpio_set()
3549 writel(0x0000007e, spec->mem_base + 0x210); in ca0113_mmio_command_set()
3550 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set()
3551 writel(0x0000005a, spec->mem_base + 0x210); in ca0113_mmio_command_set()
3552 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set()
3553 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set()
3555 writel(0x00800005, spec->mem_base + 0x20c); in ca0113_mmio_command_set()
3556 writel(group, spec->mem_base + 0x804); in ca0113_mmio_command_set()
3558 writel(0x00800005, spec->mem_base + 0x20c); in ca0113_mmio_command_set()
3563 writel(write_val, spec->mem_base + 0x204); in ca0113_mmio_command_set()
3569 readl(spec->mem_base + 0x860); in ca0113_mmio_command_set()
3570 readl(spec->mem_base + 0x854); in ca0113_mmio_command_set()
3571 readl(spec->mem_base + 0x840); in ca0113_mmio_command_set()
3573 writel(0x00800004, spec->mem_base + 0x20c); in ca0113_mmio_command_set()
3574 writel(0x00000000, spec->mem_base + 0x210); in ca0113_mmio_command_set()
3575 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set()
3576 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set()
3588 writel(0x0000007e, spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3589 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3590 writel(0x0000005a, spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3591 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3592 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3594 writel(0x00800003, spec->mem_base + 0x20c); in ca0113_mmio_command_set_type2()
3595 writel(group, spec->mem_base + 0x804); in ca0113_mmio_command_set_type2()
3597 writel(0x00800005, spec->mem_base + 0x20c); in ca0113_mmio_command_set_type2()
3602 writel(write_val, spec->mem_base + 0x204); in ca0113_mmio_command_set_type2()
3604 readl(spec->mem_base + 0x860); in ca0113_mmio_command_set_type2()
3605 readl(spec->mem_base + 0x854); in ca0113_mmio_command_set_type2()
3606 readl(spec->mem_base + 0x840); in ca0113_mmio_command_set_type2()
3608 writel(0x00800004, spec->mem_base + 0x20c); in ca0113_mmio_command_set_type2()
3609 writel(0x00000000, spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3610 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
3611 readl(spec->mem_base + 0x210); in ca0113_mmio_command_set_type2()
7712 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7713 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7714 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7715 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7716 writeb(0x00, spec->mem_base + 0x100); in ae5_post_dsp_register_set()
7717 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7718 writeb(0x00, spec->mem_base + 0x100); in ae5_post_dsp_register_set()
7719 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7720 writeb(0x00, spec->mem_base + 0x100); in ae5_post_dsp_register_set()
7721 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
7722 writeb(0x00, spec->mem_base + 0x100); in ae5_post_dsp_register_set()
7723 writeb(0xff, spec->mem_base + 0x304); in ae5_post_dsp_register_set()
8721 writeb(0x0, spec->mem_base + 0x100); in sbz_region2_exit()
8723 writeb(0xb3, spec->mem_base + 0x304); in sbz_region2_exit()
9005 writel(0x00820680, spec->mem_base + 0x01C); in sbz_pre_dsp_setup()
9006 writel(0x00820680, spec->mem_base + 0x01C); in sbz_pre_dsp_setup()
9101 writel(0x00000000, spec->mem_base + addr[i]); in ca0132_mmio_init_sbz()
9124 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); in ca0132_mmio_init_sbz()
9140 writel(data[i], spec->mem_base + addr[cur_addr + i]); in ca0132_mmio_init_sbz()
9154 writel(0x00000680, spec->mem_base + 0x1c); in ca0132_mmio_init_ae5()
9155 writel(0x00880680, spec->mem_base + 0x1c); in ca0132_mmio_init_ae5()
9164 writel(0x00800001, spec->mem_base + addr[i]); in ca0132_mmio_init_ae5()
9168 writel(data[i], spec->mem_base + addr[i]); in ca0132_mmio_init_ae5()
9172 writel(0x00880680, spec->mem_base + 0x1c); in ca0132_mmio_init_ae5()
9241 writeb(tmp[i], spec->mem_base + addr[cur_addr]); in ae5_register_set()
9248 writeb(data[i], spec->mem_base + addr[cur_addr]); in ae5_register_set()
9251 writel(data[i], spec->mem_base + addr[cur_addr]); in ae5_register_set()
9253 writel(0x00800001, spec->mem_base + 0x20c); in ae5_register_set()
9511 if (spec->mem_base) in ca0132_free()
9512 pci_iounmap(codec->bus->pci, spec->mem_base); in ca0132_free()
9921 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); in patch_ca0132()
9922 if (spec->mem_base == NULL) { in patch_ca0132()