268 		      ARRAY_SIZE(xhci->run_regs->ir_set));  in xhci_zero_64b_regs()
273 		ir = &xhci->run_regs->ir_set[i];  in xhci_zero_64b_regs()
656 	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);  in xhci_run()
663 	temp = readl(&xhci->ir_set->irq_control);  in xhci_run()
666 	writel(temp, &xhci->ir_set->irq_control);  in xhci_run()
675 	temp = readl(&xhci->ir_set->irq_pending);  in xhci_run()
678 			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));  in xhci_run()
679 	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);  in xhci_run()
753 	temp = readl(&xhci->ir_set->irq_pending);  in xhci_stop()
754 	writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);  in xhci_stop()
820 	xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);  in xhci_save_registers()
821 	xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);  in xhci_save_registers()
822 	xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);  in xhci_save_registers()
823 	xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);  in xhci_save_registers()
824 	xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);  in xhci_save_registers()
833 	writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);  in xhci_restore_registers()
834 	xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);  in xhci_restore_registers()
835 	xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);  in xhci_restore_registers()
836 	writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);  in xhci_restore_registers()
837 	writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);  in xhci_restore_registers()
1198 		temp = readl(&xhci->ir_set->irq_pending);  in xhci_resume()
1199 		writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);  in xhci_resume()