Lines Matching +full:0 +full:x150

13 #define NANDC_READ	0
15 #define RK3326_NANDC_VER	0x56393030
19 	NC_IRQ_DMA = 0,
27 	NC_BCH_70 = 0,
36 		unsigned cs : 8;		/* bits[0:7] */
149 		unsigned bch_mode : 1;	   /* 0-16bit/1KB, 1-24bit/1KB */
251 #define NANDC_FMCTL		0x0
252 #define NANDC_FMWAIT		0x4
253 #define NANDC_FLCTL		0x8
254 #define NANDC_BCHCTL		0xc
255 #define NANDC_MTRANS_CFG	0x10
256 #define NANDC_MTRANS_SADDR0	0x14
257 #define NANDC_MTRANS_SADDR1	0x18
258 #define NANDC_MTRANS_STAT	0x1c
259 #define NANDC_DLL_CTL_REG0	0x130
260 #define NANDC_DLL_CTL_REG1	0x134
261 #define NANDC_DLL_OBS_REG0	0x138
262 #define NANDC_RANDMZ_CFG	0x150
263 #define NANDC_EBI_EN		0x154
264 #define NANDC_FMWAIT_SYN	0x158
265 #define NANDC_MTRANS_STAT2	0x15c
266 #define NANDC_NANDC_VER		0x160
267 #define NANDC_LLP_CTL		0x164
268 #define NANDC_LLP_STAT		0x168
269 #define NANDC_INTEN		0x16c
270 #define NANDC_INTCLR		0x170
271 #define NANDC_INTST		0x174
272 #define NANDC_SPARE0		0x200
273 #define NANDC_SPARE1		0x230
277 	4 * x + x < 8 ? 0x20 : 0x520; })
279 #define NANDC_CHIP_DATA(id)	(0x800 + (id) * 0x100)
280 #define NANDC_CHIP_ADDR(id)	(0x800 + (id) * 0x100 + 0x4)
281 #define NANDC_CHIP_CMD(id)	(0x800 + (id) * 0x100 + 0x8)
283 #define NANDC_V9_FMCTL		0x0
284 #define NANDC_V9_FMWAIT		0x4
285 #define NANDC_V9_FLCTL		0x10
286 #define NANDC_V9_BCHCTL		0x20
287 #define NANDC_V9_MTRANS_CFG	0x30
288 #define NANDC_V9_MTRANS_SADDR0	0x34
289 #define NANDC_V9_MTRANS_SADDR1	0x38
290 #define NANDC_V9_MTRANS_STAT	0x40
291 #define NANDC_V9_MTRANS_STAT2	0x44
292 #define NANDC_V9_NANDC_VER	0x80
294 #define NANDC_V9_INTEN		0x120
295 #define NANDC_V9_INTCLR		0x124
296 #define NANDC_V9_INTST		0x128
297 #define NANDC_V9_SPARE0		0x200
298 #define NANDC_V9_SPARE1		0x204
299 #define NANDC_V9_RANDMZ_CFG	0x208
300 #define NANDC_V9_BCHST(i)	(0x150 + (i) * 4)
302 #define NANDC_V9_CHIP_DATA(id)	(0x800 + (id) * 0x100)
303 #define NANDC_V9_CHIP_ADDR(id)	(0x800 + (id) * 0x100 + 0x4)
304 #define NANDC_V9_CHIP_CMD(id)	(0x800 + (id) * 0x100 + 0x8)