Lines Matching refs:dp_lane_sel
133 u32 dp_lane_sel[4]; member
554 udphy->dp_lane_sel[0] = 0; in upphy_set_typec_default_mapping()
555 udphy->dp_lane_sel[1] = 1; in upphy_set_typec_default_mapping()
556 udphy->dp_lane_sel[2] = 3; in upphy_set_typec_default_mapping()
557 udphy->dp_lane_sel[3] = 2; in upphy_set_typec_default_mapping()
567 udphy->dp_lane_sel[0] = 2; in upphy_set_typec_default_mapping()
568 udphy->dp_lane_sel[1] = 3; in upphy_set_typec_default_mapping()
569 udphy->dp_lane_sel[2] = 1; in upphy_set_typec_default_mapping()
570 udphy->dp_lane_sel[3] = 0; in upphy_set_typec_default_mapping()
691 ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); in udphy_parse_lane_mux_data()
700 if (udphy->dp_lane_sel[i] > 3) { in udphy_parse_lane_mux_data()
705 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; in udphy_parse_lane_mux_data()
708 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { in udphy_parse_lane_mux_data()
1453 val |= BIT(udphy->dp_lane_sel[i]); in rk3588_udphy_dplane_enable()
1471 value |= 2 << udphy->dp_lane_sel[2] * 2; in rk3588_udphy_dplane_select()
1472 value |= 3 << udphy->dp_lane_sel[3] * 2; in rk3588_udphy_dplane_select()
1475 value |= 0 << udphy->dp_lane_sel[0] * 2; in rk3588_udphy_dplane_select()
1476 value |= 1 << udphy->dp_lane_sel[1] * 2; in rk3588_udphy_dplane_select()
1565 lane = udphy->dp_lane_sel[i]; in rk3588_dp_phy_set_voltages()